Auto req ID 17243BR
Job Posting Title Engineer, Principal - IC Design
Business Unit Infrastructure and Networking
Job Description This position is for DV of a very high end state of the art Optical Ethernet physical layer Serdes cores and
other networking protocol cores. In this position you will contribute to
• Play a lead role and be responsible for defining the verification strategy and plan for the development.
• Develop and execute coverage-driven verification test plans.
• Develop test suites for full chip and block level verification.
• Develop System Verilog test bench environment.
• Leverage your knowledge of constrained assertion based verification.
• Manage the regressions and analyze functional and code coverage metrics to fill the coverage holes
• Reviewing and critiquing of peers verification plan & env.
• Develop a vector matching and/or co-simulation environment to verify between C/C++ models and RTL modules.
• Add automation and scripting wherever applicable in the chip design flow
• Proactively identifying new methodologies or tools to address an upcoming verification challenges
Job Requirements • MSEE/BSEE with 10+ years in chip design verification.
• Experience in verification lead position and be able to mentor highly qualified junior staff
• Experience in planning the verification process and creating realistic schedule estimates
• Experience in System Verilog.
• Experience in scripting languages like PERL, TCL and C/C++ programming skills
• Experience in developing coverage-driven verification test plans
• Experience writing test specifications (plans) and creating directed and random test cases.
• Experience in developing constrained random verification environment
• Experience managing regression analysis
• Experience in reviewing and critiquing of test bench and test plans
• Strong debugging skills of Verilog RTL & test environment is desired
• Able to adopt the use of new techniques and methodologies and promote their use within the project.
• A high level of pro-activity, self-organized and problem solving.
• Familiarity with assertion based verification is preferred
• Verification experience in SERDES, Ethernet Networking in Verilog is a big plus.
• Knowledge of IEEE 802.3 Physical layer clauses is a plus.
Country United States
State/Province Texas
City/Town Austin
Shift 1st Shift - Day
Percent of Travel Required 5% - 10%
Function Engineering
Discipline IC Design