[{"country_short": "USA", "city": "Sunnyvale", "description": "Auto req ID 19253BR\nJob Posting Title Engineer, Sr Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom Corporation in Sunnyvale, California, USA, seeks qualified individuals for the following senior-level position (M-F 9am-6pm). Engineer, Sr. Principal \u2013 IC Design.\nWork on executing netlist to tapeout quality GDS2 for complex blocks and top-level in 28/20nm technologies. This includes floorplan, placement, power & clock design/routing, routing (X-talk & DFM aware), timing optimizations, timing closure, signoff STA (may be another tool), LVS/DRC/DFM clean database. This is a critical position that supports the SoC RTL design team in producing quality silicon working first time.\nThis senior person in the team is a mentor & technical lead for other junior members of the team.\nResponsibilities include: Developing full CAD flow for hierarchical physical design (as above).  The entire flow should be within the approved BRCM guidelines and tools.  Should be fully verified using benchmark testcases, should have top-notch QA process in place before applying to actual design projects. This person is responsible for coming up with roadmap, timelines and meeting the project requirements. Need to work with CE team and CAD vendors on all IPs & tool issues and getting them resolved in a timely fashion.\nWork on devices which contain several hundred internal memories, several millions logic gates, and high speed serial IO channels.  Responsible for full-chip or hard-modem-IP floorplan, P&R, signoff timing closure, DFM clean, tapeout quality gds2.  Work closely with RTL designer to get good quality netlists, ECOs, signoff timing closure. Responsible for tapeout quality GDS2 to be given to foundry team.\nJob Requirements Requires a BS (MS preferred) in Electrical/Electronics/Computer Engineering or related field, 18+ yrs experience, knowledge of physical design flow in 28nm or better and experience with the following computer-aided design tools: P&R tools (synopsys, Cadence, or other leading vendors), static timing analysis tools, including Synopsys Prime-Time, or Extreme DA Goldtime; formal verification tools, including Cadence LEC, or formality; LVS/DRC tools like Mentor/Calibre, Synopsys/Hercules, etc. Experience with the Unix operating system and associated utilities; Scripting languages such as Tcl/Tk, perl;\nCountry United States\nState/Province California\nCity/Town Sunnyvale\nShift 1st Shift - Day\nPercent of Travel Required 10% - 25%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-18 19:01:39", "url": "http://broadcom.jobs/xml/28794656/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Principal - IC Design", "reqid": "19253BR", "state": "California", "state_short": "CA", "location": "Sunnyvale, CA", "uid": 28794656}, {"country_short": "USA", "city": "Sunnyvale", "description": "Auto req ID 19200BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom\u2019s radio team is responsible for the design of all WLAN radio transceivers. Products include Broadcom's AirForce\u2122 product family offers the broadest line of Wi-Fi\u00ae integrated circuits in the industry for system designs ranging from PC and consumer devices to access points and routers. Broadcom's AirForce\u2122 802.11a, 802.11b, 54g\u00ae and Intensi-fi\u00ae solutions enable manufacturers to build Wi-Fi products with the performance, interoperability, security and ease-of-use that consumers and businesses demand. AirForce solutions can be found in leading brands of Wi-Fi gear such as Apple, Belkin, Buffalo, Dell, eMachines, Gateway, HP, Linksys/Cisco, and Motorola. Additionally, our design team is an integral part in Broadcom\u2019s pursuit to capture the COMBO SoC market (Combination chipsets including: Cellular, GPS, BT, NFC, FM).\n\nWe are actively seeking talented RFIC design engineers who want to join a dynamic and experienced team and take their technical knowledge to the next level in our mission of excellence. You will be responsible for the design of radios in various digital technologies including deep submicron CMOS including the design of RFIC transceiver blocks such as low noise amplifiers, power amplifiers, VGAs, mixers, RF PLLs & synthesizers and filters. You may help with transistor modeling for RF design, RF board and module design, and lab characterizations.\nJob Requirements *12+ years experience with a Bachelors, 9+ years with a Masters, or 6+ years with a PhD.\n* PhD or MS in Electrical Engineering (or equivalent) preferred\n* Expertise in RFIC CMOS designs is highly desirable.\n* Ideal candidates will have at least 2 years RF CMOS design experience in several of the following areas:\n- RF blocks used in transmitters and receivers\n- Front-end (LNA, mixers, PA drivers, PAs)\n- PLLs & Frequency Synthesizers\n- Transceivers baseband blocks (filters, VGA, ADCs & DACs)\n* Must be a self-starter, has passion for his/her work, and be able to work well in a team of RFIC design engineers.\n* System-level specification, floorplanning, characterization, and productization experience is desired.\nCountry United States\nState/Province California\nCity/Town Sunnyvale\nShift Not Applicable\nPercent of Travel Required 10% - 25%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-18 19:01:01", "url": "http://broadcom.jobs/xml/28794646/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "19200BR", "state": "California", "state_short": "CA", "location": "Sunnyvale, CA", "uid": 28794646}, {"country_short": "USA", "city": "Sunnyvale", "description": "Auto req ID 19285BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom Corporation in Sunnyvale, California, USA, seeks qualified individuals for the following senior-level position (M-F 9am-6pm). Engineer, Principal \u2013 IC Design.\nWork on executing netlist to tapeout quality GDS2 for complex blocks and top-level in 28/20nm technologies. This includes floorplan, placement, power & clock design/routing, routing (X-talk & DFM aware), timing optimizations, timing closure, signoff STA (may be another tool), LVS/DRC/DFM clean database. This is a critical position that supports the SoC RTL design team in producing quality silicon working first time.\nThis senior person in the team is a mentor & technical lead for other junior members of the team.\nResponsibilities include: Developing full CAD flow for hierarchical physical design (as above).  The entire flow should be within the approved BRCM guidelines and tools.  Should be fully verified using benchmark testcases, should be familiar with top-notch QA process for delivering tapeout quality layout.\nWork on devices which contain several hundred internal memories, several millions logic gates, and high speed serial IO channels.  Responsible for full-chip or block floorplan, P&R, signoff timing closure, DFM clean, tapeout quality gds2.  Work closely with RTL designer to get good quality netlists, ECOs, signoff timing closure. Responsible for tapeout quality GDS2 to be given to foundry team.\nJob Requirements Requires a BS (MS preferred) in Electrical/Electronics/Computer Engineering or related field, 15+ yrs experience, knowledge of physical design flow in 28nm or better and experience with the following computer-aided design tools: P&R tools (synopsys, Cadence, or other leading vendors), static timing analysis tools, including Synopsys Prime-Time, or Extreme DA Goldtime; formal verification tools, including Cadence LEC, or formality; LVS/DRC tools like Mentor/Calibre, Synopsys/Hercules, etc. Experience with the Unix operating system and associated utilities; Scripting languages such as Tcl/Tk, perl;\nCountry United States\nState/Province California\nCity/Town Sunnyvale\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-18 18:59:39", "url": "http://broadcom.jobs/xml/28794600/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "19285BR", "state": "California", "state_short": "CA", "location": "Sunnyvale, CA", "uid": 28794600}, {"country_short": "USA", "city": "Sunnyvale", "description": "Auto req ID 19480BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Join one of the hottest wireless companies in the industry. Broadcom. Leading next generation technology with products spanning the globe in segments ranging from consumer to enterprise. Be part of the world class ASIC physical design team, contributing to bringing millions of 802.11 chips to the market.\nJob Requirements Responsibility includes synthesis, floor planning, place and route, static timing analysis, IR/Em analysis, physical verification (DRC/LVS/ERC). Strong scripting skills are a plus.\nCountry United States\nState/Province California\nCity/Town Sunnyvale\nShift Any\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-17 18:21:13", "url": "http://broadcom.jobs/xml/28762662/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "19480BR", "state": "California", "state_short": "CA", "location": "Sunnyvale, CA", "uid": 28762662}, {"country_short": "USA", "city": "San Jose", "description": "Auto req ID 19449BR\nJob Posting Title Engineer, Sr Principal - IC Design\nBusiness Unit Infrastructure and Networking\nJob Description The Network Switch Division of Broadcom Corporation is well known in the networking industry for providing a wide range of world class XGS Ethernet network switching / routing chips. Our products include cutting edge 10/100Mbps, 1Gbps, 2.5Gbps, 10Gbps, 40Gbps, 100Gbps switches and fabrics that serves small to medium business, Enterprise and chassis market spaces.\n\nThis is your opportunity to be a Technical Lead within multiple disciplines in verification, and gain access to the industries latest cutting edge verification tools and methodologies. You will be challenged with owning module level verification and have the opportunity to create and develop networking industry standards.\n\nAs a senior level member of staff at Broadcom Corporation, your responsibilities will include:\n\u2022 Participate in early product definition and architecture development of our switches.\n\u2022 Fully understand architecture, microarchitecture for new design\n\u2022 Develop verification testplan for new design, build test bench, checkers, models, tests\n\u2022 Interact with design team\n\u2022 Perform RTL code coverage\n\u2022 Document and review detail testplans, testbench and close verification signoff items\n\u2022 Support post silicon activities\n\u2022 Explore and evaluate new verification methodology for adoption in our team\nJob Requirements \u2022 MSEE, with 12+ years of working experience in Verification \u2013 or equivalent experience.\n\u2022 Must have excellent knowledge and experience of ASIC design verification flows and methodologies.\n\u2022 Good knowledge in languages relevant to the ASIC verification process such as SystemVerilog (strongly preferred), Verilog, VERA, or Specman; as well as Unix Scripting, and C/C++.\n\u2022 Self-motivated, excellent communication skills and ability to excel in a team environment.\n\u2022 Experience in the Ethernet Network Switch/Fabric field is a plus.\nCountry United States\nState/Province California\nCity/Town San Jose\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-15 19:38:15", "url": "http://broadcom.jobs/xml/28707004/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Principal - IC Design", "reqid": "19449BR", "state": "California", "state_short": "CA", "location": "San Jose, CA", "uid": 28707004}, {"country_short": "USA", "city": "San Jose", "description": "Auto req ID 18802BR\nJob Posting Title Engineer, Sr Principal - IC Design\nBusiness Unit Infrastructure and Networking\nJob Description You will be a technical expert in DSP/Systems Design Engineering for High Speed Interconnect Products. You will join a team of highly competent ASIC designers involved in design, verification, and implementation (ASIC) of advanced signal processing algorithms for the physical layer of high speed copper and optical data communication networks at speeds of 25G+. The types of algorithms that will be implemented include: PAM/QAM single/multi-carrier transceivers, single/multi-input adaptive equalizers/cancelers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions.\nResponsibilities include:\n\u2022 Develop ASIC specification, architecture, and micro-architecture of signal processing and communications algorithms\n\u2022 Define and document chip requirements, architecture, verification and lab test plan\n\u2022 Bit-exact MATLAB and C/C++ system modeling and simulation\n\u2022 Develop and run system level simulation suites of the transceiver and perform vector matching verification with RTL simulations\n\u2022 Lab testing and debug of ASICs\n\u2022 Documentation/application note development and customer support\n\u2022 Attend standard committee meetings\n\u2022 Support marketing group with customer meetings and collateral\n\u2022 Good oral and written communication skills.\n\u2022 Team player, willing to take on a variety of projects, good listening skills, self motivator.\nJob Requirements \u2022 M.S.E.E./Ph.D. with 8 yrs experience\n\u2022 Expert knowledge in Communication Theory\n\u2022 Expert knowledge in Digital Signal Processing algorithms\n\u2022 Must have experience in High-Speed Communications Systems design\n\u2022 Expert in MATLAB, C/C++ programming\n\u2022 Working knowledge of Analog circuit behavior\n\u2022 Working knowledge of Transmission line theory and s-parameters\n\u2022 Good hands-on skills in the lab\n\u2022 Experience in designing high-speed Clock and Data Recovery (CDR) PLLs is a very big plus.\n\u2022 RTL coding is a plus\n\u2022 Knowledge of IEEE standards is a plus\nCountry United States\nState/Province California\nCity/Town San Jose\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-11 18:55:00", "url": "http://broadcom.jobs/xml/28634862/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Principal - IC Design", "reqid": "18802BR", "state": "California", "state_short": "CA", "location": "San Jose, CA", "uid": 28634862}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 19282BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Infrastructure and Networking\nJob Description Broadcom has led the industry migration from legacy 10/100 Fast Ethernet (FE) to Gigabit Ethernet in PCs and servers and continues to strategically invest in leading edge Ethernet technology, affording Broadcom\u2019s continued market leading success through first-to-market features, software consistency, and world-class reliability and stability.\n\nPrimary job functions will be: Physical design engineer to perform any of the following ASIC tapeout tasks:\n\u2022 ASIC design & implementation experience with specific background in the areas of timing closure, physical design, tool flow methodology\n\u2022 Minimum 10 years of experience with BSEE or 7 years with MSEE\n\u2022 Hands on experience with any of the following synthesis, static timing analysis, noise analysis, SPICE analysis\n\u2022 Hands on experience with following layout CAD tools :\n- Layout: Atoptech Aprisa or Talus\n- Synthesis: Design Compiler\n- Static timing: Primetime, Hspice\n- Noise analysis: Primetime-SI\n\u2022 Requires the ability to coding in scripting langauages, specifically TCL and unix shell languages. Others such as awk, perl, c also a plus\n\u2022 Understand layout/physical design concepts (i.e. floorplanning, power planning, power/IR/EM analysis, physical verification, custom routing, top level experience preferred)\n\u2022 Understanding of synthesis/timing closure concepts\n\u2022 Understanding of static timing and crosstalk/noise analysis\n\u2022 Write and read RTL in Verilog and/or VHDL.\n\u2022 Understanding of formal verification (i.e. formality, LEC, etc.\n\u2022 Understanding of DFT concepts\n\u2022 Ability to write/read block and chip engineering specifications.\nJob Requirements \u2022 BS in Computer Science, Computer Engineering or Electrical Engineering plus 10+ years of related experience. M.Sc. in Computer Science , Computer Engineering or Electrical Engineering is strongly desired/recommended.\n\u2022 Physical design engineer to perform any of the following ASIC design tasks:\n- Full chip level floorplanning/prototyping, integration and layout\n- Block level layout and timing closure\n- Synthesis/Physical Synthesis and timing closure\n- Static Timing/Noise/Coupling Analysis\n- Power/IR/EM analysis\n- Physical verification (LVS/DRC/ERC)\n- ECO implementation Responsibilities include:\n- Implementing tool flows and developing CAD methodologies generating flows & scripts.\n- Evaluation of tools in the development of new tool flows.\n- Responsible for managing related day to day timing closure/backend activities in meeting project schedules.\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-09 20:23:35", "url": "http://broadcom.jobs/xml/28580774/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "19282BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 28580774}, {"country_short": "USA", "city": "Sunnyvale", "description": "Auto req ID 19162BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description With a pure digital CMOS approach, Broadcom's Baseband chipsets and system solutions provide the technology to enable low-power cellular phone communication and high-speed cellular data access. Broadcom Baseband solutions offer next generation of 3G and 4G high-speed mobile technologies, with integrated high-performance application processor and advanced multimedia capability, to handle the latest in multimedia applications such as audio and video telephony, messaging, interactive gaming, location-based services and Web browsing.\n\nAs an engineering team member, you will contribute to the design, development and verification of critical IP's for baseband SOCs.\n\nResponsibilities include:\n\u2022 Participation in block level architecture design, micro-architecture and rtl coding\n\u2022 you will author detailed design documents\n\u2022 Collaboration with validation team to develop and execute thorough simulation and lab verification plans\n\u2022 Participation in the emulation platform development and pre-/post-Si lab debugging\n\u2022 Participation in design verification at block-level and chip-level\nJob Requirements Typically requires a BS degree and 12+ years of experience or an MS degree and 9+ years of\nexperience or a PhD and 6+ years of experience.\n\n\u2022 Excellent knowledge of digital design.\n\u2022 Strong analytical and problem solving skills as well as hands-on lab debugging skills.\n\u2022 Good knowledge of RTL simulation.\n\u2022 In-depth knowledge for design for low power and design for test (DFT).\n\u2022 Good Knowledge in languages relevant to the ASIC development process including Verilog / System Verilog, VHDL, Unix / Perl Scripting, and C.\n\u2022 Experience with Design Verification.\n\u2022 Experience in design and/or verification of power management for SoC is a plus.\n\u2022 Self-motivated, excellent communication skills and ability to excel in a team environment.\nCountry United States\nState/Province California\nCity/Town Sunnyvale\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-08 18:34:35", "url": "http://broadcom.jobs/xml/28540967/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "19162BR", "state": "California", "state_short": "CA", "location": "Sunnyvale, CA", "uid": 28540967}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 19219BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Office of the CTO\nJob Description We\u2019re looking for energetic, enthusiastic and driven engineers excited about high performance and low power circuits.\n\n- Knowledge of ASIC design including architecture, verification of integrated system, RTL design,\nsynthesis, and timing closure.\n- Strong experiences in different high speed/low power circuits, power management design, dynamic\ncircuit techniques and power circuit techniques.\n- Experience with complex SOC integrations, including advanced verification techniques are a must.\n- Design experience and background in low power, high speed applications.\n- Strong knowledge of architecture tradeoff analysis and modeling tools.\n- Strong working knowledge of synthesis tools.\n- Strong working knowledge of timing closure tools.\n- Strong knowledge of physical design tools (floor-planning, placement, routing, parasitic extraction)\n- Familiarities with Development of design methodology, flow automation and improvements.\nJob Requirements - Knowledge of ASIC design including architecture, verification of integrated system, RTL design,\nsynthesis, and timing closure.\n- Strong experiences in different high speed/low power circuits, power management design, dynamic\ncircuit techniques and power circuit techniques.\n- Experience with complex SOC integrations, including advanced verification techniques are a must.\n- Design experience and background in low power, high speed applications.\n- Strong knowledge of architecture tradeoff analysis and modeling tools.\n- Strong working knowledge of synthesis tools.\n- Strong working knowledge of timing closure tools.\n- Strong knowledge of physical design tools (floor-planning, placement, routing, parasitic extraction)\n- Familiarities with Development of design methodology, flow automation and improvements.\n\nEDUCATION: MSEE or PhD with 4+ years of relevant experience.\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-02 19:43:04", "url": "http://broadcom.jobs/xml/28335311/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "19219BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 28335311}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 19121BR\nJob Posting Title Engineer, Sr Principal - IC Design\nBusiness Unit Infrastructure and Networking\nJob Description A candidate will be responsible design of high speed communications integrated circuits. The job will include LSI design, generating detailed engineering specs, and leading a design team. The position will also require close interactions with team leads from other functional groups such as software, system architecture, and marketing. Overall, a candidate must be able to play a key role in developing next generation high speed controller products for consumer, enterprise client, and server markets.\nJob Requirements BSEE/MSEE/PhD 9-15 years experience in high speed communication chip architecture and chip development. Strong knowledge & background in gigabit ethernet controller is highly desired. Hands on experience in the ASIC design process; including architecture definition, spec generation, RTL design, simulation/verification, synthesis, timing closure, and silicon validation are required. Must have good communication and documentation skills. Must be a self-starter and a strong team leader. Must be proficient with major EDA tools.\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-04-25 20:32:40", "url": "http://broadcom.jobs/xml/28182264/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Principal - IC Design", "reqid": "19121BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 28182264}, {"country_short": "USA", "city": "Sunnyvale", "description": "Auto req ID 18793BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Suitable candidate will be responsible for Architecture and RTL implementation and verification of 802.11ac physical layer algorithms used in Broadcom's wireless products.\nResponsibilities:\no Work on low power/Low area H/W architecture of 802.11ac algorithms along with dsp systems. team\no Algorithm design/implementation, RTL design/implementation, pre and post-silicon validation, and chip bring-up and characterization.\no Working within a team of RTL design/verification experts and along with DSP, mixed-signal, and RF designers you will help realize complex, highly integrated ASICs\nJob Requirements MS with atleast 10 years of\nexperience in the architecture/rtl design of signal processing wireless protocols including 802.11a/b/g/n/ac.\n\nDemonstrated ability to innovate and make architectural/design trade-offs for balancing performance/power/area of designs.\nKnowledge of Verilog/VHDL languages, RTL design/verification, and of ASIC design methodology.\nKnowledge of systemC,C/C++, Perl, TCL or other scripting languages is desired.\nCountry United States\nState/Province California\nCity/Town Sunnyvale\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-04-13 19:29:42", "url": "http://broadcom.jobs/xml/27882172/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "18793BR", "state": "California", "state_short": "CA", "location": "Sunnyvale, CA", "uid": 27882172}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 18777BR\nJob Posting Title Engineer, Principal - IC Design (SoC for Ethernet Switch)\nBusiness Unit Broadband Communications\nJob Description To perform various SoC design, core integration and DFT tasks. Responsibilities includes IP core ownership, synthesis, static timing analysis, dynamic timing verification, Scan & ATPG, Logic BIST, formal verification at block, core, and chip levels.\n\n- Support integration of existing Ethernet Switch IP into new Broadcom chips.\n- Master the existing basic Ethernet Switch simulation environment and be able to run regression suites to support new chip development teams.\n- Ability to assist in debugging and resolving any issues that come up in simulation regressions.\n- Evaluate the various project requests and project specific needs, and determine the proper resolution and tracking them to completion.\n- Evaluate timing reports and assisting in closing timing at the block and chip levels.\n- Post tapeout responsibilities would include running simulations with back annotated timing for vector generation and taking them through the complete process for delivery to the test engineer, and following up with the test engineer to resolve any issues that arise when the vectors are run on the actual chip.\n- Eventually, the candidate will have full responsibility for delivering the Ethernet Switch IP to the various groups and projects through a standardized platform such as IPX, reporting directly to the appropriate chip lead.\n- Ability to expand on current test benches for existing Ethernet Switch IP. Involvement in design and development of future Ethernet Switch IP, etc.\n- Ethernet Switch knowledge and experience is highly desirable\nJob Requirements Principal Engineer typically requires a minimum BSEE and 9 years experience or MSEE and 6 years experience.\n\nKey responsibilities and accountabilities:\n1. Verilog RTL design, development, and debug.\n2. Knowledge of Ethernet Switch concepts and building blocks and interfaces a plus.\n3. Experience with large ASIC project integrations.\n4. Understanding of analog/digital interfaces and techniques.\n5. Specific knowledge of high-speed digital interfaces such as UTMI+/HSIC a plus.\n6. Project leadership and accountability a must.\n7. RTL synthesis (using Synopsys), and netlist ECO modifications.\n8. Static Timing Analysis (PrimeTime and/or Extreme DA GoldTime) at core and chip-level, including generation of all constraints and analysis of timing reports.\n9. Experience with Logic Vision\u2019s Memory (MBIST), and Logic BIST (LBIST) flow.\n10. Verification and Simulation (RTL, Gate, IKOS) at core and chip levels.\n11. Familiarity with test benches and ASIC simulation environment needed.\n12. Formal Verification (Formality, Verplex).\n13. Generation of ATE (automatic test equipment, manufacturing test) vectors for cores, including interface to the manufacturing test group.\n14. Design and verification of all DFT requirements at core and SoC levels.\n15. Interface to the layout engineers to perform all timing closure activities.\n16. Strong communication skills and willingness to work in a team environment.\n17. Attend training and to develop relevant knowledge and skills.\n18. Minimal travel required to interface with core-IP development experts, verification experts, and occasionally ATE and layout personnel.\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-04-03 21:54:11", "url": "http://broadcom.jobs/xml/27618443/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design (SoC for Ethernet Switch)", "reqid": "18777BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 27618443}, {"country_short": "USA", "city": "San Diego", "description": "Auto req ID 18366BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom is developing solutions supporting the next generation of 3G and 4G high-speed mobile technologies. As part of the CellAirity\u2122 Mobile Platform, Broadcom offers a family of HSDPA (High-Speed Downlink Packet Access), WCDMA (Wideband Code Division Multiple-Access), EDGE (Enhanced Data Rates for GSM Evolution), GPRS (General Packet Radio Services) and GSM (Global System for Mobile Communication) baseband processors for use in cellular handsets, PC cards and other wireless-enabled consumer electronics.\n\nAs wireless handsets and portable media players emerge as the dominant platform for mobile multimedia, Broadcom offers a family of mobile multimedia processors offering the ability to build next generation handheld devices supporting the latest in multimedia applications such as audio and video telephony, messaging, interactive gaming, location-based services and improved Web browsing.\n\nBroadcom is helping to build the next generation of mobile devices through our broad portfolio of industry-leading technologies for Bluetooth\u00ae, Wi-Fi\u00ae, VoIP, FM radio, DVB-H mobile TV, multimedia and other emerging technologies.\n\nIn this role you will:\nDesign and verification of blocks used in WCDMA Modem.\nDevelop and document micro-architecture of blocks used in WCDMA Modem.\nCode, debug, audit, synthesize and verify the RTL.\nParticipate in test plan creation, block and Modem level verification, and  bit exact verification of RTL with higher level models\nJob Requirements Typically requires a BS degree and 12 years of experience or an MS degree and 9 years of\nexperience or a PhD and 6 years of experience\n\n5 or more years of experience in design and verification of blocks used in implementing WCDMA modem.\n\nProficiency in RTL coding, debug, verification, and synthesis.\nExperience in optimization of signal processing micro-architectures for speed,  power and area. Experience in verification, creation of corner test cases, and code covearge.\nProfiency in VHDL/Verilog, and experience in C/C++,PERL., Matlab and TCL programming.\nA solid understanding of 3G standards is required.\nUnderstanding of underlying digital communication theory for WCDMA, HSDPA, HSUPA, CDMA, and familairity with signal processing algorithms, protocol stacks and testability is highly desirable.\nMust be well organized, methodical, detail oriented, and able to work under pressure of dead lines.\nMust have excellent interpersonal and communication skills.\nCountry United States\nState/Province California\nCity/Town San Diego\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-28 01:59:23", "url": "http://broadcom.jobs/xml/27436318/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "18366BR", "state": "California", "state_short": "CA", "location": "San Diego, CA", "uid": 27436318}, {"country_short": "USA", "city": "Sunnyvale", "description": "Auto req ID 18661BR\nJob Posting Title DFT - Principal IC Design Engineer\nBusiness Unit Mobile and Wireless Group\nJob Description Responsibilities consist of all aspects of providing a cost effective DFT solution and methodology for next generation Wireless LAN Chips.   Participation in design for testability (DFT) architecture, test strategy implementation and verification, test plan documentation, test program development and verification, ATE characterization, and transfer of test to manufacturing with ongoing sustaining support for the project assigned. Support of design, DV, synthesis, STA, and physical design on all test-related issues. Minimal travel required to interface with ATE personnel occasionally.\nJob Requirements BSEE desired, MSEE preferred 5-10+ years experience in DFT for VLSI Strong knowledge of DFT techniques - scan/atpg, logic BIST, membist, iddq, jtag. Familiarity with Verilog, VHDL, Perl, TCL Familiarity with Synthesis, Static Timing Analysis and some exposure to physical design tools. Strong experience with Logic Vision's memory and logic BIST flow desired. Experience with mixed signal a plus.\nCountry United States\nState/Province California\nCity/Town Sunnyvale\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-25 03:10:20", "url": "http://broadcom.jobs/xml/27374604/job", "country": "United States", "company": "Broadcom", "title": "DFT - Principal IC Design Engineer", "reqid": "18661BR", "state": "California", "state_short": "CA", "location": "Sunnyvale, CA", "uid": 27374604}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18117BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Broadband Communications\nJob Description Become member of a rapidly growing CPU (ARM, MIPS) and L2 Cache sub-system Design Verification team and work on the next generation CPU core DV tasks. Looking for engineers who could assist with both block level as well as chip and system level design verification tasks. You will be a member of a dedicated and highly skilled technical team with a proven track record of producing high frequency CPU cores. Growth opportunities are in leading DV tasks while working with a group of highly talented and experienced engineers in a truly mutual learning environment.\n\nKey Responsibilities:\n- Execute functional verification test plans\n- Participate in debug and coverage related tasks\n- Develop verification environment and architect test generators for block and system level test environment\nJob Requirements - BS/MS or higher in Computer Science, Electrical, Electronics or Computer Engineering\n- 5 to 8 years of prior work hands-on work experience in the DV domain\n- Knowledge of Verilog, System Verilog and/or C/C++\n- CPU and Cache Coherence Architecture knowledge a big plus\n- Verification and Simulation (RTL, Gate, Emulation) at core and chip levels\n- Assertion based, formal verification background a plus\n- Good communication skills and a team player\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift Not Applicable\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-05 18:30:19", "url": "http://broadcom.jobs/xml/26924815/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "18117BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 26924815}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18041BR\nJob Posting Title Engineer, Sr Principal - IC Design (Microprocessors)\nBusiness Unit Broadband Communications\nJob Description Primary responsibilities include:\n- Migrating existing circuit macros between process generations\n- Perform feasibility studies for new circuit macros\n- Design and implement new circuit macros using schematic capture and schematic based layout placement tools; create layout for critical nets in the design using script based layout tools.\n- Route and perform full verification on new circuit macros and custom cells, including functional, noise, EM/IR drop, and static timing analysis\n- Work with RTL and P&R teams to solve global timing paths and support any necessary changes to custom circuit macros\n- Create and maintain RTL for custom circuit macros\n- Design and implement standard cell based schematic driven layout of functional pieces of P&R blocks and associated critical nets\n- Work collaboratively with the circuit team to define and maintain design methodology flows and tools\n- Work collaboratively with the circuit team to define and implement process migration requirements and methodology\n- Interface with IP core development teams to specify and review circuit cell and memory block requirements and layout and provide feedback\n\n- Develop custom circuit macros for high frequency microprocessors as a key member of a small and motivated circuit team\n- Must be very familiar with dynamic and static circuit standard cell based design techniques, CAD tools, and verification including noise, EM/IR drop, and static timing analysis\n- Must be capable of carrying large functional blocks from feasibility studies through final verification with a high degree of independence\n- Able to vertically integrate with RTL and P&R teams\n- Can do attitude a must\n- Strong CMOS process knowledge a plus\nJob Requirements - BS degree with 15 years of experience, or MS with 12 years of experience, or PhD with 9 years of experience\n- 8+ years experience with custom and standard cell-based microprocessor designs, preferably with high volume parts\n- Extensive experience with dynamic logic and design hazards\n- Experience with high-speed memory and/or register file design and clock tree design and distribution\n- Programming skills; experience with Perl and scripting languages a plus\n- A working knowledge of Verilog\n- Familiarity with industry standard design tools and practices\n- Experience with Cadence Virtuoso schematic capture and layout tools as well as Synopsys PrimeTime and NanoTime timing tools a plus\n- High level of comfort working directly with layout at both the cell and block level\n- Good understanding of microprocessor architectural and micro-architectural issues and how they relate to custom circuit design issues\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift Not Applicable\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-01 19:35:14", "url": "http://broadcom.jobs/xml/26864891/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Principal - IC Design (Microprocessors)", "reqid": "18041BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 26864891}, {"country_short": "USA", "city": "Sunnyvale", "description": "Auto req ID 18133BR\nJob Posting Title Principal IC Design Engineer - Wireless LAN (WLAN)\nBusiness Unit Mobile and Wireless Group\nJob Description Join us and help put Wi-Fi\u00ae in everything from cell phones to TVs, and laptops to routers. Broadcom's Wireless Networking team is seeking an IC design engineer to work on our next generation 802.11 based WLAN SoCs.\n\nYou will work on design, development, and productization of WLAN SoCs to support the growing number of devices that use our Wi-Fi\u00ae chips.\n\nYour primary job responsibility is the design and verification of the wireless LAN SoCs, and the various components of the chip.\n\nIn this role you will interact with various teams - analog and digital IP providers, software, marketing, and applications teams - during various phases of the design flow.\nJob Requirements Typically requires a BSCS/BSEE degree and 8 years of related experience, an MSCS/MSEE degree and 6 years of related experience.\n\nDemonstrated ability to innovate and make architectural/design\ntrade-offs for balancing performance/power/area of designs\n\nRecent experience in SoC design flows, synthesis, timing analysis, DFT, and taking chips from concept to production is required.\n\nExperience with silicon bring-up and debugging lab/ATE issues is highly desirable.\n\nKnowledge of Verilog, System Verilog, or VHDL languages and simulation environments is required.\n\nKnowledge of Perl, Python, TCL or other scripting languages is very desirable.\n\nCandidates should have the communications skills and work habits needed to work with a geographically diverse team.\nCountry United States\nState/Province California\nCity/Town Sunnyvale\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-02-28 22:02:44", "url": "http://broadcom.jobs/xml/26822445/job", "country": "United States", "company": "Broadcom", "title": "Principal IC Design Engineer - Wireless LAN (WLAN)", "reqid": "18133BR", "state": "California", "state_short": "CA", "location": "Sunnyvale, CA", "uid": 26822445}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 17774BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom offers a family of WCDMA (Wideband Code Division Multiple-Access), EDGE (Enhanced Data Rates for GSM Evolution), GPRS (General Packet Radio Services) and GSM (Global System for Mobile Communication) products for use in cellular phones, cellular modem cards and wireless PDAs. As wireless devices including handsets, data-cards and smart-phones, emerge as the dominant platform for mobile media convergence they are driving the need for higher data rates. Broadcom is developing solutions supporting the next generation of high-speed mobile technologies with a product roadmap that includes base-band processors for WCDMA (Wideband Code Division Multiple-Access), HSDPA (High Speed Downlink Packet Access) and HSUPA (High Speed Uplink Packet Access).\n\nIn this role, you will be a member of a team of ASIC implementation experts focusing on developing and refining efficient development methodologies as well as contributing to and owning of chip implementation activities including but not limited to timing constraint development, synthesis of complex SOC subsystems, DFT insertion, static timing analysis and timing closure, coarse floorplanning, clock domain crossing verification, etc. You will use industry standard tools as well as develop custom utilities for performing these responsibilities.\n\nLocation is flexible: Will consider Sunnyvale, Irvine or San Diego, CA\nJob Requirements Typically requires a BS degree and 12 years of experience or an MS degree and 9 years of experience or a PhD and 6 years of experience.\n\n- Working knowledge of and experience in RTL (verilog, vhdl, etc) design and design techniques for SOC chips\n- Extensive experience with industry standard EDA tools including but not limited to chip synthesis, DFT, Lint, CDC, static timing analysis, floorplanning, logical equivalency checking.\n- Extensive experience in writing and verifying timing constraints for synthesis and static timing analysis.\n- ASIC design flow optimization experience a plus.\n- Working knowledge of Perl, TCL, gmake.\n- Must be well organized, methodical, and detail oriented\n- Must have excellent interpersonal and communication skills.\n- Software experience in the area of java and sql is a plus.\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required 10% - 25%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-02-14 19:41:17", "url": "http://broadcom.jobs/xml/26520144/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "17774BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 26520144}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 17656BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description As part of the GPS IC Team will do:\n- Microarchitecture and RTL Design of various blocks for SO Cs targeting portable consumer devices with a good understanding of system level issues\nJob Requirements - MSEE with minimum of 9 years experience in Microarchitecture and RTL Design for SOCs with a good understanding of system level issues\n- Experienced in working with other IP providers, marketing and system designers to come up with and efficient architecture.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-01-28 18:17:41", "url": "http://broadcom.jobs/xml/26173709/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "17656BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 26173709}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 17702BR\nJob Posting Title Principal IC Design Engineer (HDMI, DisplayPort)\nBusiness Unit Broadband Communications\nJob Description In this position you will be required to become an expert in the architectures of HDMI and DisplayPort cores for embedded system SoC. You will interface with other Business Units within Broadcom and working all the way to ensure the successful tape out of SoC products.\n\nTasks include:\n- Perform simulation, synthesis, lint, timing analysis, logic equivalent checking, area and power analysis and other design related tasks\n- Support of architecture and low-level hardware questions and issues\n- Analyze system performance, internal architectures and requirements\n- Perform lab testing of ICs and FPGA prototypes\n- Perform chip validation, board debugging and bring up\n- Provide support for investigations of internal and customer-reported issues\n- Schematic and board layout design reviews\nJob Requirements - Minimum of BSEE and 12 years of experience or MSEE and 9 years of experience\n- Verilog RTL design, RTL synthesis, Static Timing Analysis (STA)\n- Strong background in verification (system verilog, verilog, C) and validation\n- Experience with large ASIC project integrations\n- Design and verification of all DFT requirements at core and SoC levels\n- Static Timing Analysis at core and chip level, including generation of all constraints and analysis of timing reports\n- Experience with Logic Vision Memory (MBIST), and Logic Bist (LBIST) flow\n- Knowledge of lab test equipment for high-speed system and Serdes\n- Excellent debug skills in lab and in simulation\n- Knowdege of HDMI and DisplayPort will be beneficial\n- Experience in super high-speed signal integrity analysis and debug would be helpful\n- Excellent written and verbal skills willingness to work in a team environment\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-01-26 20:11:44", "url": "http://broadcom.jobs/xml/26134565/job", "country": "United States", "company": "Broadcom", "title": "Principal IC Design Engineer (HDMI, DisplayPort)", "reqid": "17702BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 26134565}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 17529BR\nJob Posting Title Engineer, Principal - IC Design (USB/SoC)\nBusiness Unit Broadband Communications\nJob Description In this position you will be required to become an expert in the architecture of USB3.0 embedded system SoC. You will interface with other Business Units within Broadcom and working all the way to ensure the successful tape out of SoC products.\n\nTasks include:\n-    Support of architecture and low-level hardware questions and issues\n-    Analyze system performance, internal architectures and requirements\n-    Perform lab testing of ICs and FPGA prototypes\n-    Perform chip validation, board debugging and bring up\n-    Provide support for investigations of internal and customer-reported issues\n-    Schematic and board layout design reviews\n-    Perform simulation, synthesis, lint, timing analysis, logic equivalent checking, area and power analysis and other design related tasks\nJob Requirements -    Minimum of BSEE and 12 years of experience or MSEE and 9 years of experience\n-    Verilog RTL design, RTL synthesis, Static Timing Analysis\n-    Strong background in verification (system verilog, verilog, OVM) and validation\n-    Experience with large ASIC project integrations\n-    Design and verification of all DFT requirements at core and SoC levels\n-    Static Timing Analysis at core and chip level, including generation of all constraints and analysis of timing reports\n-    Experience with Logic Vision Memory (MBIST), and Logic Bist (LBIST) flow\n-    Knowledge of lab test equipment for high-speed system and Serdes\n-    Excellent debug skills in lab and in simulation\n-    Knowdege of USB3.0/USB2.0 a big plus\n-    Experience in super high-speed signal integrity analysis and debug\n-    Excellent written and verbal skills willingness to work in a team environment\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-01-14 00:49:04", "url": "http://broadcom.jobs/xml/25898441/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design (USB/SoC)", "reqid": "17529BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 25898441}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 16915BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom is developing solutions supporting the next generation of 3G and 4G high-speed mobile technologies. As part of the CellAirity\u2122 Mobile Platform, Broadcom offers a family of HSDPA (High-Speed Downlink Packet Access), WCDMA (Wideband Code Division Multiple-Access), EDGE (Enhanced Data Rates for GSM Evolution), GPRS (General Packet Radio Services) and GSM (Global System for Mobile Communication) baseband processors for use in cellular handsets, PC cards and other wireless-enabled consumer electronics.\n\nIn This role, you will be responsible for RTL design/improvisations, synthesis, timing closure & support for a series of complex DRAM memory controllers.\n\nYou will be responsible for design & implementation of high speed memory interfaces like LPDDR2/LPDDR3/DDR2/DDR3 etc.\n\nThis role will include analyzing the design for performance & fixing reported issues. You will support tapeout related activities for the IP block.\nJob Requirements Typically requires a BS degree and 12 years of experience or an MS degree and 9 years of experience or a PhD and 6 years of experience.\n\n6+ yrs of industry experience in design & implementation of high speed memory interfaces like DDR1/DDR2/DDR3/LPDDR2 etc.\nYou should have very good knowledge in verilog HDL & should be well verse in using synopsys synthesis / sta tools.\nKnowledge in setting up / running spice simulation & board / substrate design experience is desirable.\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2011-11-28 23:25:43", "url": "http://broadcom.jobs/xml/25070338/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "16915BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 25070338}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 16919BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom's Baseband chipsets and system solutions provide the technology to make smart cell phone call a reality. Providing baseband, PMU, RF system and complete software support to OEMs and system integrators, Broadcom's Baseband chips enable low power cell phone communication and the wireless sharing of data among scores of electronic devices from mobile phones.\n\nAs an engineering team member, you will contribute to the design, development and verification of Broadcom's highly successful baseband SOCs.\n\nResponsibilities include:\n\u2022 Participate in block level architecture design, rtl coding\n\u2022 Author detailed design documents\n\u2022 Develop and execute thorough simulation and lab verification plan\n\u2022 Participate in the emulation platform development and lab debugging\n\u2022 Participate in synthesis, static timing analysis, DFT\nJob Requirements Typically requires BS degree and 12 years of experience or an MS degree and 9 years of experience or a PhD and 6 years of experience\n\n\u2022 Excellent knowledge of communication systems and high speed digital circuit design.\n\u2022 Strong analytical and problem solving skills as well as hands-on lab debugging skills.\n\u2022 Good knowledge of RTL simulation and synthesis.\n\u2022 In-depth knowledge for design for low power and design for test and design for manufacturing.\n\u2022 Good knowledge for standard IO interfaces including I2C, SPI, PCM, SDIO, NAND, eMMC, SLIMBus.\n\u2022 Good knowledge for ARM processor based architecture and bus protocols.\n\u2022 Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting, and C.\n\u2022 Experience with High-level Synthesis in design and verification is a plus.\n\u2022 Self-motivated, excellent communication skills and ability to excel in a team environment.\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2011-11-28 23:23:44", "url": "http://broadcom.jobs/xml/25070249/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "16919BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 25070249}]