[{"country_short": "USA", "city": "Sunnyvale", "description": "Auto req ID 19202BR\nJob Posting Title Engineer, Sr Staff - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom\u2019s radio team is responsible for the design of all WLAN radio transceivers. Products include Broadcom's AirForce\u2122 product family offers the broadest line of Wi-Fi\u00ae integrated circuits in the industry for system designs ranging from PC and consumer devices to access points and routers. Broadcom's AirForce\u2122 802.11a, 802.11b, 54g\u00ae and Intensi-fi\u00ae solutions enable manufacturers to build Wi-Fi products with the performance, interoperability, security and ease-of-use that consumers and businesses demand. AirForce solutions can be found in leading brands of Wi-Fi gear such as Apple, Belkin, Buffalo, Dell, eMachines, Gateway, HP, Linksys/Cisco, and Motorola. Additionally, our design team is an integral part in Broadcom\u2019s pursuit to capture the COMBO SoC market (Combination chipsets including: Cellular, GPS, BT, NFC, FM).\n\nWe are actively seeking talented RFIC design engineers who want to join a dynamic and experienced team and take their technical knowledge to the next level in our mission of excellence. You will be responsible for the design of radios in various digital technologies including deep submicron CMOS including the design of RFIC transceiver blocks such as low noise amplifiers, power amplifiers, VGAs, mixers, RF PLLs & synthesizers and filters. You may help with transistor modeling for RF design, RF board and module design, and lab characterizations.\nJob Requirements * BSEE w/9 yrs experience, MSEE w/6 yrs experience, or PhD EE w/3 yrs exp (PhD or MS in Electrical Engineering preferred)\n* Expertise in RFIC CMOS designs is highly desirable.\n* Ideal candidates will have at least 2 years RF CMOS design experience in several of the following areas:\n- RF blocks used in transmitters and receivers\n- Front-end (LNA, mixers, PA drivers, PAs)\n- PLLs & Frequency Synthesizers\n- Transceivers baseband blocks (filters, VGA, ADCs & DACs)\n* Must be a self-starter, has passion for his/her work, and be able to work well in a team of RFIC design engineers.\n* System-level specification, floorplanning, characterization, and productization experience is desired.\nCountry United States\nState/Province California\nCity/Town Sunnyvale\nShift Not Applicable\nPercent of Travel Required 10% - 25%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-21 18:41:30", "url": "http://broadcom.jobs/xml/28833908/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - IC Design", "reqid": "19202BR", "state": "California", "state_short": "CA", "location": "Sunnyvale, CA", "uid": 28833908}, {"country_short": "USA", "city": "San Jose", "description": "Auto req ID 19443BR\nJob Posting Title Engineer, Sr Staff - IC Design\nBusiness Unit Infrastructure and Networking\nJob Description The candidate will be part of Infrastructure and Networking team at Broadcom. He/she will focus on chip integration and design for Infrastructure and Networking products as well as ASIC products for external vendors. He/she will be exposed to state of the art chip development tools and participate in delivering products in the networking area. He/she will work on highly technically challenged tasks in all phases of the produce cycle from concept to volume production.\n\nYou will be responsible for micro-architecture and design complex Ethernet Switch memory management (MMU) and traffic management (TM) functions. Using Verilog HDL language to implement hardware, support test plan debugging efforts with design verification creating gate level netlist for physical place and route. You will also work with many cross functional team members, and enhance the design methodology.\n\nYou should also have a strong network protocol background, understanding TCP/IP traffic flow. You will leverage excellent inter-personal skills to work with a industry-leading team in IC design, architecture, marketing and applications engineering.\n\nResponsibility includes:\n- Document Micro-architecture definition and design specification\n- RTL coding, Synthesis, floor-planning analysis, timing closure with physical design team\n- work together with design verification and emulation to verify design\n-- support physical design on floor planning, resolving global and local congestion and\nclosure on static timing analysis\n-- support post silicon verification and customer failure analysis\nJob Requirements - Advance degree preferred (MS or PhD) in Electrical Engineering\n- Excellent knowledge of ASIC design flows and methodologies.\n- Must be highly motivated, and be able to work both independently and as a member of team.\n- Strong problem solving skill is a must.\n- Basic understanding of Ethernet networking concepts and protocols (layer 2, 3 and above) is a plus.\n- Familiar with Verilog/System Verilog\n- Strong experience on class of service, large number of queuing scheduling and multi-layer traffic management experience is a plus\n- Must be highly motivated, and be able to work both independently and as a member of team.\nCountry United States\nState/Province California\nCity/Town San Jose\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-15 19:37:05", "url": "http://broadcom.jobs/xml/28706981/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - IC Design", "reqid": "19443BR", "state": "California", "state_short": "CA", "location": "San Jose, CA", "uid": 28706981}, {"country_short": "USA", "city": "San Jose", "description": "Auto req ID 19292BR\nJob Posting Title Engineer, Sr Staff - IC Design\nBusiness Unit Infrastructure and Networking\nJob Description In this highly visible role, you will play a key role in designing cutting-edge high-speed network switching SOCs for Broadcom Corporation. The role is technically challenging and multidimensional in many ways. We prefer an individual that can demonstrate their technical leadership skills by bringing new initiatives in an effort to improve our RTL-to-GDS design flow and engineering process. Responsibilities include the place and route implementation , STA analysis , physical verification of high speed SOCs, clock structures and high speed memory and I/O interfaces.\n\n\nYou will utilize your hands-on skills in the following areas to design and develop our cutting-edge high-speed SOCs: clock planning, power planning, circuit analysis with IR-drop, coupling, SSO and flip chip package effects, place-and-route, parasitic extraction, timing optimization, analysis etc.\n\n\nYou will not only tape out these chips, but also contribute to enhance our reusable methodology and flow. Additional responsibilities include interacting with the product design teams, as well as the internal IP and library groups.\nJob Requirements Hands on experience with physical design and analysis tools from Synopsys/Cadence/Atoptech/Mentor/Apache , along with good understanding of overall RTL-to-GDS flow , circuit analysis , STA timing concepts is required. Good scripting skills in Perl and Tcl are also required.\nCountry United States\nState/Province California\nCity/Town San Jose\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-15 09:56:11", "url": "http://broadcom.jobs/xml/28699214/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - IC Design", "reqid": "19292BR", "state": "California", "state_short": "CA", "location": "San Jose, CA", "uid": 28699214}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 16284BR\nJob Posting Title Engineer, Sr Staff - IC Design (P&R Physical Design)\nBusiness Unit Mobile and Wireless Group\nJob Description Our chip team designs giant mobile apps processor SOC's for smartphones, tablets, and the mobile computing market. In 2011, Broadcom became the 5th largest mobile apps processor vendor, surpassing Nvidia. We expect to continue that trend up the rankings with your help!\n\nhttp://www.eetimes.com/electronics-news/4231160/Broadcom-slips-into-top-5-in-smartphone-CPUs\n\nOur group contains ASIC engineers with all the skills required to design a chip from spec through tapeout and bring-up. Our group has a start-up's excitement to it, with the stability of a world leading semiconductor company.\n\nOur latest chip contains dual 1.2GHz ARM CPU's + world leading multimedia + cellular modem + a multitude of other blocks/interfaces. With our next chip, we are aiming for the high end of the market, so come join us, and work on a really exciting chip!\n\nWe are currently hiring multiple physical design engineers. Strong domain knowledge in any of these areas is especially interesting to us:\n\nPhysical design implementation at block or top level, low power techniques and timing closure.\n\nJob Duties Include:\n\n- Will own all parts of the physical design process from netlist handoff to tapeout including floorplanning, place and route, clock tree synthesis, timing closure and physical verification\n- Verify effects of crosstalk, IR drop and electromigration\n- Very comfortable writing scripts in TCL and Perl to achieve higher performance and productivity through automation\n- Work very closely with logic designers, who are members of this same group, to build complex SOC's you'll be proud of\nJob Requirements - BSEE with 9+ years related experience or MSEE with 6+ years related experience\n- Physical design knowledge, from netlist handoff to GDS tapeout including floorplanning, place and route, clock tree synthesis, timing closure and physical verification\n- Experience with 45nm or 28nm technology\n- Experience with low power techniques\n- Experience with TCL and Perl\n- Excellent communication and presentation skills\n- Well organized, methodical and detail oriented\n- Must be a team player and easy to work with\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-04-07 05:42:32", "url": "http://broadcom.jobs/xml/27722321/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - IC Design (P&R Physical Design)", "reqid": "16284BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 27722321}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18763BR\nJob Posting Title IC Design (RTL Design and Verification) - Engineer, Sr Staff\nBusiness Unit Mobile and Wireless Group\nJob Description With a pure digital CMOS approach and excellent RF performance, Broadcom's WPAN chipsets and system solutions provide the technology to make wireless personal area networking a reality. Providing radio frequency, baseband, system and complete software support to OEMs and system integrators, Broadcom's WPAN chips enable the wireless sharing of data among scores of electronic devices, from mobile phones and wireless stereo headsets to PDAs and automobiles.\n\nAs a senior engineering team member, you will contribute to the design, development and verification of Broadcom's highly successful Wireless Personal Area Network (PAN) SOCs. Responsibilities include: \u2022 Lead the block level architecture design \u2022 Author detailed design documents \u2022 Develop and execute thorough simulation and lab verification plan \u2022 Participate in the emulation platform development and lab debugging \u2022 Participate in synthesis, static timing analysis, DFT \u2022 Assist in the development of embedded FW.\n\n- Location is flexible, will consider San Diego, CA and Santa Clara, CA.\nJob Requirements \u2022 BS degree and 9 years of experience or an MS degree and 6 years of experience or a PhD and 3 years of experience is preferable\n\u2022 Excellent knowledge of communication systems and high speed digital circuit design.\n\u2022 Strong analytical, and problem solving skills as well as hands-on lab debugging skills.\n\u2022 Excellent knowledge of RTL design and verification.\n\u2022 Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix Scripting, and C.\n\u2022 Working experience needs to demonstrate the technical expertise in successful completion of multiple VLSI projects.\n\u2022 Experience with the following areas in design and verification is a plus:\no Advanced Constrained-random functional verification methodology such as OVM/UVM/VMM and/or SV Assertion\no Systems using communication systems/protocols such as 802.11, PCIe, USB3, SDIO and HDMI\n\u2022 Self-motivated, excellent communication skills and ability to excel in a team environment.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-04-07 05:42:09", "url": "http://broadcom.jobs/xml/27722315/job", "country": "United States", "company": "Broadcom", "title": "IC Design (RTL Design and Verification) - Engineer, Sr Staff", "reqid": "18763BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27722315}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 17991BR\nJob Posting Title Engineer, Sr Staff - IC Design (HDMI, DisplayPort)\nBusiness Unit Broadband Communications\nJob Description In this position you will be required to become an expert in the architectures of HDMI and DisplayPort cores for embedded system SoC. You will interface with other Business Units within Broadcom and working all the way to ensure the successful tape out of SoC products.\n\nTasks include:\n- Perform simulation, synthesis, lint, timing analysis, logic equivalent checking, area and power analysis and other design related tasks\n- Support of architecture and low-level hardware questions and issues\n- Analyze system performance, internal architectures and requirements\n- Perform lab testing of ICs and FPGA prototypes\n- Perform chip validation, board debugging and bring up\n- Provide support for investigations of internal and customer-reported issues\n- Schematic and board layout design reviews\nJob Requirements - Minimum of BSEE and 9 years of experience or MSEE and 6 years of experience\n- Verilog RTL design, RTL synthesis, Static Timing Analysis (STA)\n- Strong background in verification (system verilog, verilog, C) and validation\n- Experience with large ASIC project integrations\n- Design and verification of all DFT requirements at core and SoC levels\n- Static Timing Analysis at core and chip level, including generation of all constraints and analysis of timing reports\n- Experience with Logic Vision Memory (MBIST) and Logic Bist (LBIST) flow\n- Knowledge of lab test equipment for high-speed system and Serdes\n- Excellent debug skills in lab and in simulation\n- Knowdege of HDMI and DisplayPort will be beneficial\n- Experience in super high-speed signal integrity analysis and debug would be helpful\n- Excellent written and verbal skills willingness to work in a team environment\nCountry United States\nState/Province California\nCity/Town Irvine\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-02-22 18:35:51", "url": "http://broadcom.jobs/xml/26679418/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - IC Design (HDMI, DisplayPort)", "reqid": "17991BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 26679418}, {"country_short": "USA", "city": "Irvine", "description": "Auto req ID 17815BR\nJob Posting Title Engineer, Sr Staff - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom's Baseband chipsets and system solutions provide the technology to make smart cell phone call a reality. Providing baseband, PMU, RF system and complete software support to OEMs and system integrators, Broadcom's Baseband chips enable low power cell phone communication and the wireless sharing of data among scores of electronic devices from mobile phones.\n\nAs an engineering team member, you will contribute to the design, development and verification of Broadcom's highly successful baseband SOCs.\n\nResponsibilities include:\n\u2022 Participate in block level architecture design, rtl coding\n\u2022 Author detailed design documents\n\u2022 Develop and execute thorough simulation and lab verification plan\n\u2022 Participate in the emulation platform development and lab debugging\n\u2022 Participate in synthesis, static timing analysis, DFT\nJob Requirements Typically requires a BS degree and 9 years of experience or an MS degree and 6 years of experience or a PhD and 3 years of experience.\n\u2022 Degree in Electrical or Computer Engineering Preferred.\n\u2022 Excellent knowledge of communication systems and high speed digital circuit design.\n\u2022 Strong analytical and problem solving skills as well as hands-on lab debugging skills.\n\u2022 Good knowledge of RTL simulation and synthesis.\n\u2022 In-depth knowledge for design for low power and design for test and design for manufacturing.\n\u2022 Good knowledge for standard IO interfaces including I2C, SPI, PCM, SDIO, NAND, eMMC, SLIMBus.\n\u2022 Good knowledge for ARM processor based architecture and bus protocols.\n\u2022 Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting, and C.\n\u2022 Experience with High-level Synthesis in design and verification is a plus.\n\u2022 Self-motivated, excellent communication skills and ability to excel in a team environment.\nCountry United States\nState/Province California\nCity/Town Irvine\nShift Not Applicable\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-02-14 19:41:59", "url": "http://broadcom.jobs/xml/26520167/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - IC Design", "reqid": "17815BR", "state": "California", "state_short": "CA", "location": "Irvine, CA", "uid": 26520167}, {"country_short": "USA", "city": "Sunnyvale", "description": "Auto req ID 17776BR\nJob Posting Title Engineer, Sr Staff - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom offers a family of WCDMA (Wideband Code Division Multiple-Access), EDGE (Enhanced Data Rates for GSM Evolution), GPRS (General Packet Radio Services) and GSM (Global System for Mobile Communication) products for use in cellular phones, cellular modem cards and wireless PDAs. As wireless devices including handsets, data-cards and smart-phones, emerge as the dominant platform for mobile media convergence they are driving the need for higher data rates. Broadcom is developing solutions supporting the next generation of high-speed mobile technologies with a product roadmap that includes base-band processors for WCDMA (Wideband Code Division Multiple-Access), HSDPA (High Speed Downlink Packet Access) and HSUPA (High Speed Uplink Packet Access).\n\nIn this role, you will be a member of a team of ASIC implementation experts focusing on chip implementation activities including but not limited to timing constraint development, synthesis of complex SOC subsystems, DFT insertion, static timing analysis and timing closure, coarse floorplanning, clock domain crossing verification, etc. You will use industry standard tools as well as develop custom utilities for performing these responsibilities.\n\nLocation is flexible: Will consider Sunnyvale, Irvine or San Diego, CA\nJob Requirements Typically requires a BS degree and 9 years of experience or an MS degree and 6 years of experience or a PhD and 3 years of experience.\n\n- Working knowledge of and experience in RTL (verilog, vhdl, etc) design and design techniques for SOC chips\n- Extensive experience with industry standard EDA tools including but not limited to chip synthesis, DFT, Lint, CDC, static timing analysis, floorplanning, logical equivalency checking.\n- Extensive experience in writing and verifying timing constraints for synthesis and static timing analysis.\n- ASIC design flow optimization experience a plus.\n- Working knowledge of Perl, TCL, gmake.\n- Must be well organized, methodical, and detail oriented\n- Must have excellent interpersonal and communication skills.\n- Software experience in the area of java and sql is a plus.\nCountry United States\nState/Province California\nCity/Town Sunnyvale\nShift 1st Shift - Day\nPercent of Travel Required 10% - 25%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-02-14 19:41:26", "url": "http://broadcom.jobs/xml/26520149/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - IC Design", "reqid": "17776BR", "state": "California", "state_short": "CA", "location": "Sunnyvale, CA", "uid": 26520149}]