Auto req ID 17327BR
Job Posting Title Engineer, Sr Staff - IC Design
Business Unit Broadband Communications
Job Description - Support integration of existing USB3.0/USB2.0/1.1 IP into new Broadcom chips.
- Master the existing basic USB simulation environment and be able to run regression suites to support new chip development teams.
- Ability to assist in debugging and resolving any issues that come up in simulation regressions.
- Evaluate the various project requests and project specific needs, and determine the proper resolution and tracking them to completion.
- Evaluate timing reports and assisting in closing timing at the block and chip levels.
- Post tapeout responsibilities would include running simulatons with back annotated timing for vector generation and taking them through the complete process for delivery to the test engineer, and following up with the test engineer to resolve any issues that arise when the vectors are run on the actual chip.
- Eventually, the candidate will have full responsibility for delivering the USB IP to the various groups and projects through a standardized platform such as IPX, reporting directly to the appropriate chip lead.
- Ability to expand on current test benches for existing USB IP. Involvement in design and development of future USB IP, etc.
Job Requirements To perform various SoC design, core integration and DFT tasks. Responsibilities includes IP core ownership, synthesis, static timing analysis, dynamic timing verification, Scan & ATPG, Logic BIST, formal verification at block, core, and chip levels.

Key responsibilities and accountabilities:
1. Verilog RTL design, development, and debug.
2. Knowledge of USB concepts and protocols and interfaces a plus.
3. Experience with large ASIC project integrations.
4. Understanding of analog/digital interfaces and techniques.
5. Specific knowledge of high-speed digital interfaces such as UTMI+/HSIC a plus.
6. Project leadership and accountability a must.
7. RTL synthesis (using Synopsys), and netlist ECO modifications.
8. Static Timing Analysis (PrimeTime and/or Extreme DA GoldTime) at core and chip-level, including generation of all constraints and analysis of timing reports.
9. Experience with Logic Vision’s Memory (MBIST), and Logic BIST (LBIST) flow.
10. Verification and Simulation (RTL, Gate, IKOS) at core and chip levels.
11. Familiarity with test benches and ASIC simulation environment needed.
12. Formal Verification (Formality, Verplex).
13. Generation of ATE (automatic test equipment, manufacturing test) vectors for cores, including interface to the manufacturing test group.
14. Design and verification of all DFT requirements at core and SoC levels.
15. Interface to the layout engineers to perform all timing closure activities.
16. Strong communication skills and willingness to work in a team environment.
17. Attend training and to develop relevant knowledge and skills.
18. Minimal travel required to interface with core-IP development experts, verification experts, and occasionally ATE and layout personnel.
Country India
State/Province India Cities
City/Town Hyderabad
Shift 1st Shift - Day
Percent of Travel Required 5% - 10%
Function Engineering
Discipline IC Design