[{"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 19544BR\nJob Posting Title Staff Engineer - Processor DFT & Design\nBusiness Unit Infrastructure and Networking\nJob Description The candidate chosen for this position will be working in the Multi-Core XLP Processor Development team, where cutting edge, industry leading designs are underway.\n\nHere you will be verifying high-quality test logic to allow easy, efficient, and effective testing and debug of chips as they move from prototype to production, helping to improve silicon yield, and improving team efficiency by automation and other techniques.\n\nYou will be exposed to multiple disciplines as a regular part of your daily job: logic design, verification, validation, test methodologies, silicon engineering.\n\nYou\u2019ll be expected to use good inter-personal skills to work across organizations to achieve the goals set with your manager.\n\nYou will be the major contributor to the RTL-level and gate-level verification efforts for the memory BIST, JTAG, and boundary scan logic for this family of products.\n\nYou will interact closely with logic design team and operations team.\n\nResponsibilities:\n\n\u2022  Be self-motivated to develop a good understand of the memory BIST, JTAG, and boundary scan logic features on the chips, and their resulting verification challenges.\n\n\u2022  Maintain the existing memory BIST and JTAG boundary scan test-benches. Enhance the test-benches by adding new features, improving quality and scalability. Document the test-benches to make them more usable by logic designers and new employees.\n\n\u2022  Set up the infrastructure to run weekly and monthly regressions for the test logic. Actively debug and drive the debug of failures. Track and report test-logic RTL quality over project lifetime. Identify corner cases that are not being covered, and enhance regressions to cover them.\nJob Requirements \u2022  MS EE degree.\n\n\u2022  2-3 years of recent, relevant experience are preferred.\n\n\u2022  Strong Verilog coding and comprehension skills are required.\n\n\u2022  Strong knowledge of logic design techniques is required. Actual prior logic design experience is a plus.\n\n\u2022  Prior scripting experience with Perl is required or have ability to pick it up quickly.\n\n\u2022  Basic knowledge of RAM and register file internal circuitry and organization is required.\n\n\u2022  Prior verification experience is a plus.\n\n\u2022  Prior experience with memory BIST (MBIST) algorithms, JTAG, or boundary scan is required\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-23 19:56:09", "url": "http://broadcom.jobs/xml/28895473/job", "country": "United States", "company": "Broadcom", "title": "Staff Engineer - Processor DFT & Design", "reqid": "19544BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28895473}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 19164BR\nJob Posting Title Principal FPGA Engineer - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description This position is responsible for all activities necessary to plan and complete major engineering projects involving complex digital logic designs using FPGA devices for GPS products.\u00a0\n\u2022 Lead efforts in selection of digital logic devices, implementation and verification.\n\u2022 Modification of ASIC RTL designs to utilize FPGA resources efficiently\n\u2022 Partitioning design across multiple FPGAs using standard tool flows .\n\u2022 Work with ASIC team on creating FPGA Verification environment\n\u2022 Work with SW engineers to enable early SW/FW development\n\u2022 Ensure that layout, power supplies and I/O allocations will provide a sound FPGA implementation.\n\u2022 Collaborate and provide leadership within board level design\nJob Requirements \u2022 BSEE w/12+ yrs exp, MSEE 9+ yrs exp, or PhD EE w/6+ yrs experience.\n\u2022 Candidate should have 7+ years experience in hardware development, delivering multiple successful products to market\n\u2022 Follows a sound development process and adheres to industry best practices, including source code control, defect tracking, and code review\n\u2022 Very high technical competence, and proven track record for high quality and on time product delivery\n\u2022 Requires solid knowledge of digital high-speed design, timing, electrical analysis and system-level issues.\n\u2022 Experience with lab bring up and design validation of products.\n\u2022 Experience with embedded CPU SOCs and related debugging tools highly desirable.\n\u2022 Have well-rounded knowledge of various types of EDA tools such as schematic capture, simulation, synthesis, place-and-route tools.\n\u2022 Familiarity with Synplify Pro, backend Xilinx and Altera tools a plus.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-21 18:42:55", "url": "http://broadcom.jobs/xml/28833962/job", "country": "United States", "company": "Broadcom", "title": "Principal FPGA Engineer - IC Design", "reqid": "19164BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28833962}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 19029BR\nJob Posting Title DFT/Timing Principal IC Design Engineer\nBusiness Unit Mobile and Wireless Group\nJob Description Job Description\nAs a member of the GPS ASIC Implementation team, the candidate will be responsible for\n\u2022 Working independently with the RTL design team on understanding and implementing the flow required to achieve the testability goals of complex ICs\n\u2022 Developing the DFT infrastructure for complex SOCs\n\u2022 Helping develop and implement the flow required to achieve Timing Closure in DFT mode\n\u2022 Working with Test Engineering on silicon bringup on ATE using at-speed test and self-test flow\nJob Requirements - BSEE w/12+ yrs exp, or MSEE w/9+ yrs exp, or PhD EE w/6+ yrs experience.\n\u2022 Must have 7-10 years in DFT on complex chips using industry standard DFT flows, preferably from Mentor Graphics\n\u2022 Must have full-speed test and self-test flow experience\n\u2022 Must have SI-aware Timing Analysis and Closure experience\n\u2022 DFT experience (LogicVision suite of tools) is highly desirable\n\u2022 Must be highly motivated, and able to work independently and as a member of a team\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-21 18:41:32", "url": "http://broadcom.jobs/xml/28833910/job", "country": "United States", "company": "Broadcom", "title": "DFT/Timing Principal IC Design Engineer", "reqid": "19029BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28833910}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 19150BR\nJob Posting Title Engineer, Sr Staff - Software Applications\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom provides industry-leading A-GPS technology to the mobile wireless industry. Our semiconductor solutions bring IndoorGPS\u00ae technology to the full spectrum of mobile wireless devices, including handsets, smartphones, tablets and other wireless devices. Our A-GPS network infrastructure products and data services power the global location services of our mobile operator customers.\n\nAs part of the GPS systems and applications team, this experienced system or software engineer will be responsible for accelerating the adoption and integration of GPS and related connectivity semiconductor products.\n\nReporting into the BU AE Manager and working with various cross-functional teams, this individual will have as his / her main responsibility contributing to the development of Windows (8) platform software and engaging in all aspects of the technical support for tablet/notebook as well as handset manufacturers and silicon platform providers integrating the Broadcom A-GPS chipset and software into their early prototypes and commercial products.\n\nDuties and Responsiblities include:\n\u2022 Design, develop and test/debug software applications and device drivers for the core host-based GPS library targeting Windows 8, including full support of A-GPS protocols and sensors.\n\u2022 Provide in-depth support in resolving complex software, hardware, and systems issues (eg. board bring-up, performance testing) interfacing directly with customers\n\u2022 Analyse core GNSS performance and resolve any issues in cooperation with core R&D team\n\u2022 Give advice in wireless communication standards related to A-GPS as well as technical support during Interoperability Tests with Network Equipment vendors or even live cellular networks\n\u2022 Coordinate with Hardware AE team to perform schematic reviews and layout analysis\n\u2022 Review and write system application notes, product specifications, and test reports according to internal and customer requirements\n\u2022 Work within applications engineering, with other business units and customers to generate and promote sample applications, system level documentation and evaluation/analysis tools\n\u2022 Work with R&D feeding back customer requirements, market information and issues that can enhance our products\nJob Requirements \u2022 BSEE or BSCS degree with 9 or more years of experience or MSEE or MSCS degree with 6 or more years of applicable experience, or PhD in EE or CS with 3 or more years of experience\n\u2022 Windows middleware, user-mode and/or kernel driver development\n\u2022 Native application development using ATL/WTL, boost, STL libraries\n\u2022 Some experience using .Net framework desirable\n\u2022 Knowledge of Windows Embedded CE/Windows Mobile\n\u2022 Additional knowledge of Android/Linux (or embedded platforms) are a plus\n\u2022 Proven recent skills in software programming in (C/)C++, C# (and Java), HTML5/XML and Javascript would be nice supplements\n\u2022 Solid understanding (and demonstrated application) of object-oriented design and analysis principles,\napplication of design patterns\n\u2022 Previous experience with GPS receivers and/or protocols used with Assisted GPS are a plus\n\u2022 Ability to operate lab test equipment and basic knowledge of digital hardware and radio frequency concepts\n\u2022 Basic comprehension of hardware schematics/layouts\n\u2022 Understanding of wireless systems in general (Bluetooth, mobile telephony)\n\u2022 Self-reliant, self-motivated, able to work multiple tasks under pressure and to tight timescales.\n\u2022 Ability to successfully interact with customers, good presentation skills and willingness to travel\n\u2022 Excellent oral and written communication skills in English\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 10% - 25%\nFunction Engineering\nDiscipline Software Applications", "date_new": "2012-05-21 18:40:26", "url": "http://broadcom.jobs/xml/28833896/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - Software Applications", "reqid": "19150BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28833896}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 19330BR\nJob Posting Title Engineer, Principal - Software Systems\nBusiness Unit Broadband Communications\nJob Description We are looking for a talented BS or MS candidate to work with our Santa Clara team to develop and support leading edge Set-top Box Technologies for our worldwide customers in the areas of HDTV, MPEG2/H.264, PVR, IPSTB.\nJob Requirements \u2022 BS or MS in Computer Science or equivalent\n\u2022 Strong programming skills in C/C++\n\u2022 The candidate should have working experience with real-time OS\u2019s and embedded systems\n\u2022 Previous work with application and driver software development on one or more embedded operating systems would be highly desirable\n\u2022 Prior experience with ARM, MIPS or other microprocessor architecture and tools is desirable\n\u2022 Experience with MPEG audio/video\n\u2022 Excellent organizational skills, self-driven\n\u2022 Strong logical and creative problem-solving skills, good oral and written communication skills, excellent analytical skills and teamwork capabilities\n\u2022 Some (5-10%) domestic or international travel may be required\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift Not Applicable\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline Software Systems", "date_new": "2012-05-18 19:00:16", "url": "http://broadcom.jobs/xml/28794613/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - Software Systems", "reqid": "19330BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28794613}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 19438BR\nJob Posting Title Sr Staff Product Engineer\nBusiness Unit Operations/QA\nJob Description (1) Responsible for transferring product from Development to Volume Production per schedule. This includes reliability qualification and product Characterization, Data Analysis and Report Generation.\n(2) Interface with Internal (Marketing, Design, Manufacturing Groups) and External (Customer, Vendors) Groups.\n(3) Drive Cost reduction, Yield improvement projects\n(4) Support Package/Process Qualification\n(5) Customer Support (product issues, customer reports,customer meetings)\nJob Requirements - Minimum BSEE required + 6 years of experience\n- Strong communication skills\n- Strong problem solving skills\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline Product Engineering", "date_new": "2012-05-15 19:35:22", "url": "http://broadcom.jobs/xml/28706845/job", "country": "United States", "company": "Broadcom", "title": "Sr Staff Product Engineer", "reqid": "19438BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28706845}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 19343BR\nJob Posting Title Network Engineer - CISCO\nBusiness Unit Information Services\nJob Description This employee will be a member of the Information Technology Network team and will work with various functional areas on gathering requirements, evaluating, designing, implementing, and supporting network (LAN, MAN, WAN, wireless, VPN, content networking) technologies that will enable the organization to work effectively and productively. The employee will define, document and implement strategy, direction and architectures for the global network environment. This requires extensive and broad functional experience with switching, routing, firewall, VPN, wireless, content networking, and network management systems across a wide range of complex architectures, platforms and mediums.  CHARACTERISTIC DUTIES AND RESPONSIBILITIES:  * Research, design, plan, and implement new network technologies into current operating environment. Test and evaluate future looking technologies by participating in beta tests of given technologies. * Look for ways to provide enhancements to existing network services. Make recommendations, define the ROI, and implement these improvements using an accepted change control methodology process. * Define and follow standards and best practices for network design, testing, and implementation methodology. Document the environment.  * Configure, deploy, fine-tune, monitor, maintain, upgrade, troubleshoot, support and repair the Broadcom global network as required. Provide training to regional site staff for same.\nJob Requirements QUALIFICATIONS:  * 5+ years of direct engineering and design experience in the telecommunications and/or networking industry.  Cisco CCNP/CCDP or CCIE certifications preferred. * Expertise in creating repeatable, reliable, scalable network architectures, with fault tolerance, performance tuning, monitoring systems, statistics/metrics collection, and disaster recovery. Expert working knowledge (including the ability to setup, configure, upgrade, manage, and troubleshoot) Cisco routers, switches, VPN concentrators, firewalls, 802.11 wireless access points, and load balancers. * Understanding of transport protocols, routing protocols, and security/authentication protocols at all layers of the OSI model with emphasis on TCP/IP are essential. * Must have knowledge networking features and protocols such as spanning tree, ARP, CDP, EIGRP, RIP, OSPF, BGP, VTP, Etherchannel, 802.1Q trunking, MLS, HSRP, QoS, multicast, 802.11, IPsec, Frame Relay, RADIUS/TACACS+, SNMP, T-1/E-1, BRI/PRI, MPLS, dial-up services, and caching services. * Additional areas of expertise in areas such as VoIP, DSL, BlueTooth, dial-up, and cable access desired. * Experience with network management tools such as Sniffers, Ethereal, MRTG, HP Openview, Whats Up Gold, Netreo Omniscient. Sniffer certification or CNX a plus. * Experience supporting Windows and UNIX products systems/applications on networking technologies. Certifications and/or experience equivalent to MCSE, Solaris, and Linux are a bonus. * Ability to learn new things quickly, and need minimal direction. * A high degree of creative ability, analytical and technical skills and independent judgment/decision making. * Good strategic planning, project management, organizational and time management skills to handle multiple complex enterprise-scale complex projects simultaneously. * Excellent communications and presentation skills and candidate must have the ability to communicate with internal/external customers, vendors, management etc. in both formal and informal situations. * Strong interpersonal skills needed to team well with peers, customers, project managers, and vendors.  SUPERVISION RECEIVED:  Performs under the general direction of the Manager of Network Infrastructure. Must be self motivated, and self directed.  SUPERVISION EXERCISED:  Be able to manage vendors, consultants, or peer team members to fulfill the above functions and responsibilities.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 10% - 25%\nFunction IT\nDiscipline Network Engineer", "date_new": "2012-05-10 19:10:29", "url": "http://broadcom.jobs/xml/28606929/job", "country": "United States", "company": "Broadcom", "title": "Network Engineer - CISCO", "reqid": "19343BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28606929}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 19276BR\nJob Posting Title Principal Test Engineer (ATE/Mixed Signal)\nBusiness Unit Operations/QA\nJob Description - Responsibilities include all aspects of providing a production test solution for mixed signal product lines\n- Will team with Design and Product Engineering to assess testability, develop and implement test strategies, document test plans, develop ATE test programs and hardware, correlate tester and bench measurements, provide ATE characterization data, and transfer test manufacturing, offering ongoing sustaining support for each assigned project\nJob Requirements - BSEE required, MSEE preferred\n- 12+ years experience with high-speed mixed signal testers (Teradyne UFlex (IGXL) or Verigy 93K required)\n- Mixed signal knowledge required\n- Strong programming background (C++, Visual Basic, Perl)\n- Knowledge of high-speed SerDes and network product test methodologies desired\n- Knowledge of DFT (scan, iddq, jtag), DSP, Analog Test Methodology, Linux and Windows\n- Must be a good communicator, team player, have project planning/organizational skills, and demonstrate analytical thinking\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Operations\nDiscipline Test", "date_new": "2012-05-08 18:35:21", "url": "http://broadcom.jobs/xml/28540999/job", "country": "United States", "company": "Broadcom", "title": "Principal Test Engineer (ATE/Mixed Signal)", "reqid": "19276BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28540999}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18823BR\nJob Posting Title Manager DFT - Multi-Core Processors\nBusiness Unit Infrastructure and Networking\nJob Description The DFT Manager will improve and enhance our DFT methodology to become efficient and process-automated.\n\nThis person will manage a team of engineers in a fast-paced organization working on leading-edge processor technology.\n\nKey Responsibilities:\n\n\u2022  Define DFT Methodology and architecture.\n\n\u2022  Write DFT specifications.\n\n\u2022  Lead the team on BIST/JTAG insertion and verification.\n\n\u2022  Manage gate level DFT verification, pattern generation and silicon debug support.\n\n\u2022  Oversee block level and chip level ATPG for advanced fault models.\nJob Requirements \u2022  10-15 years of relevant DFT industry experience.\n\n\u2022  5 years of experience managing teams.\n\n\u2022  MS or PhD in EE/CS\n\n\u2022  Knowledge of Perl/Tcl scripting.\n\n\u2022  Strong experience in Logic design (Verilog), verification and static timing analysis.\n\n\u2022  Experience with multi-million and high speed and low power designs.\n\n\u2022  Experience with industry standard DFT tools.\n\n\u2022  Familiarity with high speed circuit design and tradeoffs.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-05-02 19:49:04", "url": "http://broadcom.jobs/xml/28335542/job", "country": "United States", "company": "Broadcom", "title": "Manager DFT - Multi-Core Processors", "reqid": "18823BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28335542}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 19129BR\nJob Posting Title Sr Staff Product Engineer\nBusiness Unit Operations/QA\nJob Description Support of NetLogic products like multi-core CPU, KBP, DFE and media processors.\n\n(1) Responsible for transferring product from Development to Volume Production per schedule. This includes reliability qualification and product Characterization, Data Analysis and Report Generation.\n(2) Interface with Internal (Marketing, Design, Manufacturing Groups) and External (Customer, Vendors) Groups.\n(3) Drive Cost reduction, Yield improvement projects\n(4) Support Package/Process Qualification\n(5) Customer Support (product issues, customer reports,customer meetings)\nJob Requirements - Minimum MSEE required + 6 years of experience\n- Strong communication skills\n- Strong problem solving skills\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline Product Engineering", "date_new": "2012-05-01 18:28:56", "url": "http://broadcom.jobs/xml/28302505/job", "country": "United States", "company": "Broadcom", "title": "Sr Staff Product Engineer", "reqid": "19129BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28302505}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18734BR\nJob Posting Title Engineer, Staff I - Software Systems\nBusiness Unit Mobile and Wireless Group\nJob Description Broadcom provides industry-leading A-GNSS technology to the mobile wireless industry. Our semiconductor solutions bring IndoorGPS\u00ae technology to the full spectrum of mobile wireless devices, including handsets, smartphones, PDAs and other wireless devices. Our A-GNSS network infrastructure products and data services power the global location services of our mobile operator customers.\n\nWe are currently hiring talented engineers who will be responsible for doing performance, functionality and regression testing on GNSS/Location sensors hardware and software systems. Please note that this position requires Android experience.\nJob Requirements - 1+ years of GPS/Location sensors software test experience\n- Experience with Spirent GPS simulators and equipment\n- Experience with Android\n- Good software skills including experience in writing scripts (Perl, Java etc.)\n- Excellent documentation skills, highly organized, and extreme attention to detail\n- Ability to travel 30%\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 25% - 50%\nFunction Engineering\nDiscipline Software Systems", "date_new": "2012-04-28 18:01:30", "url": "http://broadcom.jobs/xml/28258366/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Staff I - Software Systems", "reqid": "18734BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28258366}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18115BR\nJob Posting Title CPU Verification Lead/Manager\nBusiness Unit Broadband Communications\nJob Description Become a key member of Embedded Processor (MIPS/ARM) Design Verification team. Work on the next generation ARM processor core. Looking for a senior Processor DV lead who could lead/manage the Design verification, block level as well as chip-level simulation and verification tasks. You will be a member of a dedicated and highly skilled technical team with a proven track record of producing high frequency CPU cores. Growth opportunities are in leading DV tasks while working with a group of highly talented, innovative and experienced engineers in a truly mutual learning environment.\n\nKey responsibilities and accountabilities are some of the following:\n- Work with the Architect and RTL design team to generate Functional Test Plans for the assigned blocks\n- Participate and drive the verification infrastructure development, debug and coverage tasks\n- Work with onsite and offshore teams to drive/lead/manage various DV tasks\n- Develop verification environment and architect test generators for block level and chip level\n\nJob Requirements:\n- BS/MS or higher in Electrical Engineering, Computer Science, or Computer Engineering\n- Minimum 10+ years experience in Design Verification (CPU environment)\n- Prior Processor Verification Lead/Management experience is desirable\n- Experience with cache coherence verification is desirable\n- Well organized, methodical, and detail oriented\n- Good communication skills and willingness to work in a team environment\nJob Requirements - BS/MS or higher in Electrical Engineering, Computer Science, or Computer Engineering\n- Minimum 10+ years experience in Design Verification (CPU environment)\n- Prior Processor Verification Lead/Management experience is desirable\n- Experience with cache coherence verification is desirable\n- Well organized, methodical, and detail oriented\n- Good communication skills and willingness to work in a team environment\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift Not Applicable\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-04-24 20:19:50", "url": "http://broadcom.jobs/xml/28151214/job", "country": "United States", "company": "Broadcom", "title": "CPU Verification Lead/Manager", "reqid": "18115BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 28151214}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 17907BR\nJob Posting Title Media Framework Software Engineer\nBusiness Unit Broadband Communications\nJob Description Develop key components for Broadcom\u2019s Application Software product that enables Broadcom Settop boxes to be part of a Digitally Connected Home and provides capabilities for Open Web access and Over the Top streaming. Port key frameworks such as Android, Webkit , Flash or Broadcom\u2019s Application Frameworks to leverage underlying hardware acceleration for video decoding/transcode, Open GL acceleration, DRM, Networking and other areas\nJob Requirements Bachelors or Master\u2019s in Computer science with 8+years of related experience in developing software components for Digital Entertainment devices with focus on areas such as graphics and video acceleration and IP streaming . Must have expertise programming in C and C++ and good understanding of Object Oriented design. Experience with developing or porting Webkit, Android or other 3rd party frameworks to Settop Boxes or Digital TVs highly desired. Experience with porting 3rd party DRMs is a plus\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline Software Systems", "date_new": "2012-04-17 20:06:01", "url": "http://broadcom.jobs/xml/27953038/job", "country": "United States", "company": "Broadcom", "title": "Media Framework Software Engineer", "reqid": "17907BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27953038}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18853BR\nJob Posting Title Engineer, Sr Staff - Product Applications\nBusiness Unit Mobile and Wireless Group\nJob Description The industry\u2019s most respected fabless communications semiconductor, software and systems innovator, Broadcom, is looking for the world\u2019s best and brightest engineers. As one of Fortune magazine\u2019s Most Admired Companies\u201d, Broadcom promotes an open work environment, embracing change, taking risks and doing the impossible every day.\nOutstanding initiative and aggressive execution is at the core of who and what we are, and we take pride in outdoing, outsmarting and outselling the competition.\n\nWith the fifth most valuable patent portfolio in the world and through the hard work and dedication of our people, Broadcom achieves a leadership position in every market we enter. If you have a passion for advancing technology, then we encourage you to apply for this exciting opportunity.\n\n* Provide applications support to customers for designs\n* Review customers\u2019 implementations of board designs\n* Test, characterize and optimize product performance on customers\u2019 board designs\n* Assist in the customer transition to high volume manufacturing\n* Define specifications to work with Broadcom Controller IC's Establish and manage supplier partnerships\n* Design, develop and assemble demo hardware systems as needed\n* Work with internal chip and firmware/software engineering to debug and verify new chips and reference boards\n* Write Application Notes and Datasheets\n* Train FAEs in product applications\nJob Requirements * BSEE degree and 5 years of related experience, or an MSEE degree and 3 years of related experience\n* Experience in board design, test, characterization, debug and system performance testing\n* Strong hands on skills and good working knowledge of test and verification equipment\n* Experience with schematic capture, layout and related CAD tools is a plus\n* Strong team-player and practical problem solver to work with internal chip and firmware/software engineering\n* Strong verbal and written communication skills\n* Ability to work through technical issues with customers is required\n* Familiarity with Cell Phone & Embedded architectures\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline Product Applications", "date_new": "2012-04-13 19:27:22", "url": "http://broadcom.jobs/xml/27882128/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - Product Applications", "reqid": "18853BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27882128}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18763BR\nJob Posting Title IC Design (RTL Design and Verification) - Engineer, Sr Staff\nBusiness Unit Mobile and Wireless Group\nJob Description With a pure digital CMOS approach and excellent RF performance, Broadcom's WPAN chipsets and system solutions provide the technology to make wireless personal area networking a reality. Providing radio frequency, baseband, system and complete software support to OEMs and system integrators, Broadcom's WPAN chips enable the wireless sharing of data among scores of electronic devices, from mobile phones and wireless stereo headsets to PDAs and automobiles.\n\nAs a senior engineering team member, you will contribute to the design, development and verification of Broadcom's highly successful Wireless Personal Area Network (PAN) SOCs. Responsibilities include: \u2022 Lead the block level architecture design \u2022 Author detailed design documents \u2022 Develop and execute thorough simulation and lab verification plan \u2022 Participate in the emulation platform development and lab debugging \u2022 Participate in synthesis, static timing analysis, DFT \u2022 Assist in the development of embedded FW.\n\n- Location is flexible, will consider San Diego, CA and Santa Clara, CA.\nJob Requirements \u2022 BS degree and 9 years of experience or an MS degree and 6 years of experience or a PhD and 3 years of experience is preferable\n\u2022 Excellent knowledge of communication systems and high speed digital circuit design.\n\u2022 Strong analytical, and problem solving skills as well as hands-on lab debugging skills.\n\u2022 Excellent knowledge of RTL design and verification.\n\u2022 Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix Scripting, and C.\n\u2022 Working experience needs to demonstrate the technical expertise in successful completion of multiple VLSI projects.\n\u2022 Experience with the following areas in design and verification is a plus:\no Advanced Constrained-random functional verification methodology such as OVM/UVM/VMM and/or SV Assertion\no Systems using communication systems/protocols such as 802.11, PCIe, USB3, SDIO and HDMI\n\u2022 Self-motivated, excellent communication skills and ability to excel in a team environment.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-04-07 05:42:09", "url": "http://broadcom.jobs/xml/27722315/job", "country": "United States", "company": "Broadcom", "title": "IC Design (RTL Design and Verification) - Engineer, Sr Staff", "reqid": "18763BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27722315}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18761BR\nJob Posting Title Product Applications Engineer - Knowledge-based Processors\nBusiness Unit Infrastructure and Networking\nJob Description As an Applications Engineer for Knowledge-based Processors (KBPs), you will be responsible for cross-discipline technical and product expertise. In this position, you will be required to become an expert in KBPs as well as the supporting hardware and technologies that ensure proper operation of the processors. You will use this expertise to provide technical support to key networking infrastructure OEMs to ensure successful launch of the finished products.\n\nYou will provide technical guidance to customers' ASIC engineers from simulation to device bring-up. You will play a key role in working with customers' board design engineers, providing guidance on schematic and layout, power distribution network, thermal budgeting, and signal integrity (among others), ensuring that the processor is properly designed into the customers' systems. You will also guide the customers' SW engineers to optimize for maximum performance with the lowest power consumption.\n\nInternal engineering activities include high-speed board design from concept to bring up. You will participate in system definition, board-level design (FPGA selection, clock and power distribution, multi-phase power supplies, decoupling, etc.), schematic capture, signal integrity analysis, layout review, FPGA design definition (clock distribution, resource analysis, pinout, etc.), RTL design / modification, and software-test infrastructure definition / implementation.\n\nOther duties include assisting sales team in technical communications, product training, device analysis, and other technical problem solving. There are unique challenges in working with Knowledge-based Processors, and you will have the opportunity to expand your technical knowledge in both breadth and depth. You will also work with a variety of internal employees in IC design and verification engineering, software engineering, architecture, field applications engineering, sales, marketing, production and test engineering, manufacturing, and senior management.\n\nDuties of this position:\n\u2022 Support of architecture and low-level hardware questions and issues\n\u2022 Schematic and layout reviews\n\u2022 Customer board bring-up assistance and debug\n\u2022 Debugging complicated issues, including coordinating internal activities, to resolve the problem\n\u2022 Pre-sales and post-sales support via e-mail, phone, and customer visits\n\u2022 Customer and FAE training\n\u2022 Support documents: Datasheets and Application Notes\nJob Requirements \u2022 BSEE/MSEE or similar\n\u2022 Minimum 3 to 5 years in comparable support role with a strong track record of success\n\u2022 High-speed SERDES expertise\n\u2022 Power delivery network (supply to decoupling) design and analysis\n\u2022 High-speed board design and bring up experience\n\u2022 RTL design / implementation experience with FPGAs\n\u2022 Solid understanding of digital IC\n\u2022 Fluent with lab equipment\n\u2022 Project and time management skills\n\u2022 Strong team player and practical hands on problem solver\n\u2022 Customer-facing aptitude\n\u2022 Excellent written and oral communications skills\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 10% - 25%\nFunction Engineering\nDiscipline Product Applications", "date_new": "2012-04-05 04:26:09", "url": "http://broadcom.jobs/xml/27658182/job", "country": "United States", "company": "Broadcom", "title": "Product Applications Engineer - Knowledge-based Processors", "reqid": "18761BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27658182}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18684BR\nJob Posting Title Senior Staff Digital Design Engineer- Multi-Ghz Processor\nBusiness Unit Infrastructure and Networking\nJob Description We are looking for self-motivated individuals who can blend ingenuity and logical problem solving skills to optimize critical components of a multi-giga hertz processor which will be designed on a next generation foundry process technology.\n\nResponsibilities include:\n\nInteracting with the architecture team to develop a physical implementation that can meet the schedule, power, frequency and area design targets.\n\nImplementing the function using custom design techniques and enhanced synthesis methodology\n\nInsuring circuit based design specifications are met: setup and hold timing, slew rates, noise, signal and power EM, dynamic and static IR, right sizing of devices, VT and gate length selection, thermal heating, power budgeting,\nJob Requirements \u2022  BSEE/MSEE\n\n\u2022  Practical experience in all steps required to convert RTL into foundry ready GDS for a high speed CPU in a leading edge process, sub 40 nanometer\n\n\u2022  5+ years experience with processor implementation or custom circuit design and key contributor on several product design cycles\n\n\u2022  Extensive RTL/physical design background with knowledge of datapath design and floorplanning a must\n\n\u2022  Solid understanding of circuit fundamentals, computer architecture, and microprocessor design\n\n\u2022  Sufficient coding skills to independently develop automation and parsing scripts\n\n\u2022  Demonstrated problem solving and communication skills as well as a proven abilty to work well within a team\n\n\u2022  Familiar with the back end tool suites from the large EDA vendors ( RTL, synthesis, schematic capture, circuit simulation, timing closure(STA), equivalency check, P&R, power estimation, DFT, extraction, timing, post layout verification )\n\n\u2022  Proficient coding skills \u2013 PERL, C, C++, SKILL, TCL, Shell Scripting; familiar with Linux/Unix environment\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-04-05 04:26:00", "url": "http://broadcom.jobs/xml/27658178/job", "country": "United States", "company": "Broadcom", "title": "Senior Staff Digital Design Engineer- Multi-Ghz Processor", "reqid": "18684BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27658178}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18822BR\nJob Posting Title Principal DSP Engineer\nBusiness Unit Infrastructure and Networking\nJob Description This individual will be responsible for advanced algorithm development, behavioral modeling, architectural development, cost-performance tradeoff analysis, test vector generation and technical documentation and will generate fixed point models of transceivers, correlate results with lab measurements, and generate test vectors for IC design team.\n\nThe work will focus on all signal processing functions needed in wireless infrastructure (eg. DPD, CFR, DUC, DDC, channel equalization, etc.).\nJob Requirements \u2022 Master's degree in electrical engineering with concentration in signal processing required\n\n\u2022 Minimum of 10 years of experience in the communications semiconductor industry\n\n\u2022 Experience with adaptive filtering, statistical signal processing modulation schemes, channel modeling, noise characterization and error correction theory required\n\n\u2022 Working knowledge and hands on experience in both wired and wireless communications highly desirable\n\n\u2022 Educational background in statistical and adaptive signal processing and communication theory, information theory, systems theory, and filter design essential\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline DSP", "date_new": "2012-04-05 04:24:39", "url": "http://broadcom.jobs/xml/27658145/job", "country": "United States", "company": "Broadcom", "title": "Principal DSP Engineer", "reqid": "18822BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27658145}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18693BR\nJob Posting Title Technical Lead CPU Verification- Multi-Core Processor\nBusiness Unit Infrastructure and Networking\nJob Description The successful candidate will be a well-rounded verification engineer with a solid computer architecture background, responsible for infrastructure development and verification of a multi-core, multi-threaded network processor.\n\nResponsibilities:\n\n\u2022  Define/Setup/develop infrastructure for verification of a high performance CPU at a core level.\n\n\u2022  Work closely with architects/RTL engineers to bring up a new architecture/micro-architecture on the verification environment.\n\n\u2022  Verify of one or more blocks of a high performance CPU both architecturally and micro-architecturally\n\n\u2022  Understand micro-architecture of the block/s to be verified, and develop and execute testplans for the same.\n\n\u2022  Own and debug failures in simulation to root-cause problems\n\n\u2022  Work closely with RTL engineers of block being verified for test plan development, execution, and debug\nJob Requirements \u2022  BS (EE or CS) required with 10-16 years relevant experience. Master\u2019s level preferred\n\n\u2022  Strong verification skills including a good knowledge of different methodologies such as:\n\no Architecture versus Micro-architecture level\n\no Random versus Directed testing\n\no Full-chip versus Module-level\n\n\u2022  Good CPU architecture/micro-architecture knowledge:\n\no MIPS, PowerPC, ARM, x86 or SPARC architectures\n\no CPU pipeline\n\no  Out-of-order execution, superscalar and caches\n\n\u2022  Working knowledge and experience on Verilog\n\n\u2022  Strong programming background on C++ and/or System Verilog.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-28 01:58:49", "url": "http://broadcom.jobs/xml/27436310/job", "country": "United States", "company": "Broadcom", "title": "Technical Lead CPU Verification- Multi-Core Processor", "reqid": "18693BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27436310}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18718BR\nJob Posting Title Manager - Product Applications - Multi-Core Processors\nBusiness Unit Infrastructure and Networking\nJob Description Seeking motivated and independent candidate to lead a team of 5-8 Applications Engineers while simultaneously managing multiple projects.\n\nThe Applications team assists Broadcom FAEs in supporting customers using our multicore products and software development kits through the various aspects of their evaluation and design cycles, including bringup, debug and optimization of complex applications, and development of application notes and other written guidance to the users of the products.\n\nThe team responsibilities also include development and maintenance of demo applications, tools and diagnostics to complement existing software.\nJob Requirements -  BSCS/BSEE + 12 years or MSCS/MSEE + 9 years in Applications Engineering or Software development\n\n-  3+ years of Team and Project Management experience\n\n-  Knowledge of Operating Systems internals\n\n-  Working knowledge of CPU architecture\n\n-  SMP experience is desired\n\n-  RTOS or Embedded SW experience is desired\n\n-  Experience in networking protocol stack is desired\n\n-  Device driver experience is desired\n\n-  Strong communication skills\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 10% - 25%\nFunction Engineering\nDiscipline Product Applications", "date_new": "2012-03-28 01:58:46", "url": "http://broadcom.jobs/xml/27436309/job", "country": "United States", "company": "Broadcom", "title": "Manager - Product Applications - Multi-Core Processors", "reqid": "18718BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27436309}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18692BR\nJob Posting Title Principal Digital Design Engineer- Multi-Ghz Processor\nBusiness Unit Infrastructure and Networking\nJob Description We are looking for self-motivated individuals who can blend ingenuity and logical problem solving skills to optimize critical components of a multi-giga hertz processor which will be designed on a next generation foundry process technology.\n\nResponsibilities include:\n\nInteracting with the architecture team to develop a physical implementation that can meet the schedule, power, frequency and area design targets.\n\nImplementing the function using custom design techniques and enhanced synthesis methodology\n\nInsuring circuit based design specifications are met: setup and hold timing, slew rates, noise, signal and power EM, dynamic and static IR, right sizing of devices, VT and gate length selection, thermal heating, power budgeting,\nJob Requirements \u2022 BSEE/MSEE\n\n\u2022 Practical experience in all steps required to convert RTL into foundry ready GDS for a high speed CPU in a leading edge process, sub 40 nanometer\n\n\u2022 10 to 12 years experience with processor implementation or custom circuit design and key contributor on several product design cycles\n\n\u2022 Extensive RTL/physical design background with knowledge of datapath design and floorplanning a must\n\n\u2022 Solid understanding of circuit fundamentals, computer architecture, and microprocessor design\n\n\u2022 Sufficient coding skills to independently develop automation and parsing scripts\n\n\u2022 Demonstrated problem solving and communication skills as well as a proven abilty to work well within a team\n\n\u2022 Familiar with the back end tool suites from the large EDA vendors ( RTL, synthesis, schematic capture, circuit simulation, timing closure(STA), equivalency check, P&R, power estimation, DFT, extraction, timing, post layout verification )\n\n\u2022 Proficient coding skills \u2013 PERL, C, C++, SKILL, TCL, Shell Scripting; familiar with Linux/Unix environment\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-28 01:58:08", "url": "http://broadcom.jobs/xml/27436298/job", "country": "United States", "company": "Broadcom", "title": "Principal Digital Design Engineer- Multi-Ghz Processor", "reqid": "18692BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27436298}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18546BR\nJob Posting Title Principal Physical Design Engineer - Low Power Innovator\nBusiness Unit Infrastructure and Networking\nJob Description We are seeking a bright, self-motivated individual who is capable of learning quickly on the job. This position will support RTL, verification, physical design, circuit design and post-silicon teams to bring power efficiency across the entire product design cycle.\n\nResponsibilities will include full ownership of power estimation and reduction. The chosen candidate must be able to do intelligent planning, have a solid understanding of all aspects of VLSI designs, and be able to give technical presentations.\n\nThe role will have very high visibility on a complex, cutting edge VLSI Multi-Core Processor team operating in 40nm and 28nm process nodes.\n\nRESPONSIBILITIES :\n\n\u2022 Ownership of power distribution methodology and low power implementation across multiple projects.\n\n\u2022 Define low power methodology and run fullchip verification of power grids\n\n\u2022 Run cycle accurate power simulations on RTL and gate views\n\n\u2022 Develop methodology and tools for leakage recovery and power reduction.\n\n\u2022 Drive front-end power reduction\n\n\u2022 Post-silicon power validation\nJob Requirements \u2022  MSEE or PhD\n\n\u2022  9+ years directly related physical design expertise in state of the art ICs with emphasis on VLSI physical design and methodology on 45 or 28 nanometer process nodes\n\n\u2022  Must have a proven track record of delivering tape-out quality GDSII with silicon success\n\n\u2022  Wide range of prior design experience including RTL, physical design, digital and analog circuit design, chip finishing and silicon validation\n\n\u2022  Experience with Place and Route, STA, Clock, Power and Noise analysis.\n\n\u2022  Strong hands on familiarity with VCS or Incisive, Power Artist, Design Compiler, Calibre, Hspice, LEC, Formality, Primetime SI, Redhawk and StarRC preferred\n\n\u2022  Proficiency using Perl, TCL.\n\n\u2022  Must be able to proactively drive and solve problems to solutions.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-20 21:01:58", "url": "http://broadcom.jobs/xml/27273383/job", "country": "United States", "company": "Broadcom", "title": "Principal Physical Design Engineer - Low Power Innovator", "reqid": "18546BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27273383}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18449BR\nJob Posting Title SoC Architect/ Senior Principal Engineer - Digital Front End (DFE)\nBusiness Unit Infrastructure and Networking\nJob Description The exponential growth in mobile data traffic in the next decade, coupled with global spectrum scarcity, are forcing service providers and operators worldwide to push the limits on capacity and throughput for their limited spectrum.\n\nThis is in turn driving a need for next-generation base stations that can support dramatically wider bandwidth, significantly more signal channels and more protocols (2G/3G/4G) in each band.\n\nBroadcom's best-in-class DFE processors are highly differentiated and ideally suited to address these challenging LTE requirements.\n\nThese processors deliver unparalleled performance of up to 5X increase in signal bandwidth and up to 9X increase in instantaneous bandwidth over available competing solutions, which dramatically improves 3G/4G LTE data rates.\n.\nThis is a senior principal architect position in our DFE ASIC development team, engaged in developing single chip solutions for Remote Radio Heads.\n\nIn this role you will work closely with our Systems, SW, and HW engineering teams and own the architecture of our next generation DFE ASIC SOC.\n\nResponsibilities:\n\n\u2022 Translate technical requirements into detailed architectural specifications that are implementable.\n\n\u2022 Define architecture of a high performance bus that integrates embedded processors, DRAM and a number of on-chip peripherals\n\n\u2022 Define and maintain the address mapping of all programmable resources on the device\n\n\u2022 Work closely with the system\u2019s team to validate hardware feasibility of various requirements collected from customers.\n\n\u2022 Keep a top-level view of how various resources within the device communicate with one another and ensure inter-operability between different interfaces.\n\n\u2022 Own the verification test plan and oversee test creation to ensure coverage on the device.\n\n\u2022 Work closely with DSP engineers to define required vectors to validate various arithmetic and DSP functions within the device.\n\n\u2022 Act as the first level interface to describe and support various functions of the device to various entities like marketing, systems, applications etc\n.\n\u2022 Work closely with Software team to partition critical functions between h/w and s/w.\n\n\u2022 Engage with Software team to develop BSP and Driver development.\nJob Requirements \u2022 MSEE with about 12 years industry experience\n\n\u2022 Must have strong expertise with ARM/MIPS based SOCs\n\n\u2022 Prior proven experience of having architected at least one major SOC that is in volume production.\n\n\u2022 Experience with DDR DRAMs\n\n\u2022 Prior experience with Logic or System design\n.\n\u2022 Experience with: CPRI, OBSAI, 10GE, 1588, MPLS etc. a major plus.\n\n\u2022 Knowledge of HW/Firmware partitioning a plus\n\n\u2022 Working knowledge of behavioral simulation environments a plus.\n\n\u2022 Excellent written and verbal communications.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-15 19:38:47", "url": "http://broadcom.jobs/xml/27171970/job", "country": "United States", "company": "Broadcom", "title": "SoC Architect/ Senior Principal Engineer - Digital Front End (DFE)", "reqid": "18449BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27171970}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18466BR\nJob Posting Title Senior Staff Digital Design Engineer- Memory Subsystem\nBusiness Unit Infrastructure and Networking\nJob Description One chip- 20 CPUs, 80 threads and 100 Gbps networking. That is just part of Broadcom\u2019s aggressive multi-core processor roadmap now.\n\nThis is an opportunity to work on the team that is creating some of the fastest multi-core, multi-threaded processors on the market.\n\nOur goal is and will continue to be to develop leading edge processors at the top of the power and performance curve.\n\nResponsibilites:\n\n\u2022  Design units for the following in the memory sub-system:\no  Cache coherency\no  Cache controllers\no  Memory controllers\no  On-chip interconnect\no  Inter-chip interfaces\n\n\u2022  Develop the micro-architecture specification and implement the Verilog RTL code for the blocks\n\n\u2022  Assist verification team in developing appropriate test bench, test plan & tests.\n\n\u2022  Assist physical/circuit design team for implementation\n\n\u2022  Assist systems team for board design & debug\n\n\u2022  Evaluate and provide feedback for IP selection.\nJob Requirements \u2022 BSEE/MSEE/PhD with 5-10 years experience\n\n\u2022 Strong knowledge of computer architecture and exposure high speed digital circuit design\n\n\u2022 Experience with cache coherency, cache controllers, memory controllers, memory subsystem, onchip-interconnects, interchip interfaces a big plus\n\n\u2022 Knowledge of Verilog, Perl, Synopsys, Static timing analysis, Multi-clock domain synchronization, System Verilog assertions, scripting\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-15 19:38:20", "url": "http://broadcom.jobs/xml/27171960/job", "country": "United States", "company": "Broadcom", "title": "Senior Staff Digital Design Engineer- Memory Subsystem", "reqid": "18466BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27171960}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18491BR\nJob Posting Title MEMS Sr. Product Line Manager\nBusiness Unit Mobile and Wireless Group\nJob Description - Work with strategy and corporate development teams to understand new markets and technologies\n- Ramp up on new technologies and markets and become resident expert in a very short period of time\n- Establish analytical frameworks and conduct complex business analysis for new emerging markets\n- Perform quantitative and qualitative analysis including market sizing, competitive analysis and ROI\n- Synthesize large sets of information, extract insights, and develop recommendations to management team\n- Collaborate and develop effective working relationships with diverse set of internal and external stakeholders\n- Develop executive level presentations and reports\nJob Requirements - Bachelor degree in Electrical Engineering or Science\n- Minimum of 7 years of experience in Product Marketing/Technical Marketing\n- Subject matter expertise in one or more of the following areas: MEMS sensors, mobile phone semiconductors and systems, or consumer electronics semiconductor and systems\n- Deep understanding of semiconductor process flow, costs and pricing models\n- Outstanding analytical (qualitative and quantitative), research, and presentation skills\n- Excellent presentation skills with ability to interface with all levels of management internal and external\n- Strong interpersonal, communication and team building skills\n- Ability to thrive in ambiguous and rapidly changing environment\n- Highly motivated to achieve desired goals and objective\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Marketing\nDiscipline Product Marketing", "date_new": "2012-03-15 19:37:11", "url": "http://broadcom.jobs/xml/27171942/job", "country": "United States", "company": "Broadcom", "title": "MEMS Sr. Product Line Manager", "reqid": "18491BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27171942}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18431BR\nJob Posting Title Senior Staff System Emulation Engineer\nBusiness Unit Infrastructure and Networking\nJob Description This is your chance to broaden your chip and system view as a member of the Multi-core Processor Group.\n\nThe Multi-core XLP Network Processor has been touted An Exceptional CPU, well beyond the capabilities of other embedded processors\u201d by The Microprocessor Report.\n\nYou will be directly responsible for all aspects of hardware emulation of a complex CPU/SOC.\n\nResponsibilities:\n\n\u2022 Infrastructure development and bring-up of a multi-core CPU/SOC in hardware emulation (Cadence palladium)\n\n\u2022 Develop methodology/tool flow for running assembly tests/SW applications/boot OS on hw emulator\n\n\u2022 Setup regression flow on the same for testing out different areas of the chip\n\n\u2022 Use hw emulator effectively to test out various areas of the chip along with hw/sw co-simulation\n\n\u2022 Help reproduce post-silicon failures on hw emulator and help with reproduction of failures in hw emulator on simulation.\n\n\u2022 Closely work with RTL/verification engineers for debug and root-cause\nJob Requirements \u2022 Prior experience with hardware emulation (EVE, Cadence Palladium/Xtreme, Mentor Veloce, Synopsys HAPS, other FPGA/ASIC-based emulator) of a high-performance processor or SOC\n\n\u2022 Strong background in system integration and trouble-shooting\n\n\u2022 Strong programming (C/C++) and scripting skills (Perl, Python, etc)\n\n\u2022 Prior experience with methodology development for hardware emulation\n\n\u2022 Good working knowledge of Verilog, System Verilog and assembly programming\n\n\u2022 Self-motivated team player with excellent problem solving skills\n\u2022 BS (EE or CS) required with 3-8 years relevant experience. MS (EE or CS) preferred\n\n\u2022 Past experience with Cadence Palladium hardware emulator is a plus\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-11 23:58:42", "url": "http://broadcom.jobs/xml/27063991/job", "country": "United States", "company": "Broadcom", "title": "Senior Staff System Emulation Engineer", "reqid": "18431BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27063991}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18354BR\nJob Posting Title Principal System Architect - Digital Front End (DFE)\nBusiness Unit Infrastructure and Networking\nJob Description The exponential growth in mobile data traffic in the next decade, coupled with global spectrum scarcity, are forcing service providers and operators worldwide to push the limits on capacity and throughput for their limited spectrum.\n\nThis is in turn driving a need for next-generation base stations that can support dramatically wider bandwidth, significantly more signal channels and more protocols (2G/3G/4G) in each band.\n\nBroadcom's best-in-class Digital Front End (DFE) processors are highly differentiated and ideally suited to address these challenging LTE requirements. These processors deliver unparalleled performance of up to 5X increase in signal bandwidth and up to 9X increase in instantaneous bandwidth over available competing solutions, which dramatically improves 3G/4G LTE data rates.\n\nThis is a principal level architect position in the DFE development team, engaged in developing single chip solutions for Remote Radio Heads.\nIn this role you will work closely with our Marketing, ASIC, SW, and HW engineering teams and our System test team with a \"cradle to grave\" charter for the high speed baseband interface.\n\nKey responsibilities include:\n\n\u2022 Translate market requirements into technical requirements.\n\n\u2022 Define architecture for high speed baseband interface, switching fabric and interconnect with rest of system\n\n\u2022 Define system hardware software partitioning to achieve low latency, high throughput and high degree of flexibility.\n\n\u2022 Drive system engineering aspects from product conception through implementation.\n\n\u2022 Support product bringup with heavy emphasis on lab debug, performance and functional qualification.\n\n\u2022 Define Product conformance/qualification test plans and criteria, support testing with timely resolution of issues found.\n\n\u2022 Oversee and support interoperability engagements and field trials, with timely resolution of issues found.\n\n\u2022 Provide technical marketing support\nJob Requirements \u2022 MSEE and a minimum of 10 years industry experience\n\u2022 Expert knowledge high speed serial communication and networking over optical and copper.\n\u2022 Expert knowledge of precision timing, clock recovery and distribution.\n\u2022 Experience with: CPRI, OBSAI, 10GE, 1588, MPLS.\n\u2022 Experience with internal SoC interconnect.\n\u2022 Experience with hardware vs. firmware partitioning\n\u2022 Experience with hardware packet accelerators, switching and distribution.\n\u2022 Experience DMA, hardware FIFO\u2019s and efficient h/w, s/w handoff.\n\u2022 Platform design considerations: eg. optical module selection, PCB layout considerations, etc.\n\u2022 Excellent written and verbal communications.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-11 23:55:44", "url": "http://broadcom.jobs/xml/27063983/job", "country": "United States", "company": "Broadcom", "title": "Principal System Architect - Digital Front End (DFE)", "reqid": "18354BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 27063983}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18117BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Broadband Communications\nJob Description Become member of a rapidly growing CPU (ARM, MIPS) and L2 Cache sub-system Design Verification team and work on the next generation CPU core DV tasks. Looking for engineers who could assist with both block level as well as chip and system level design verification tasks. You will be a member of a dedicated and highly skilled technical team with a proven track record of producing high frequency CPU cores. Growth opportunities are in leading DV tasks while working with a group of highly talented and experienced engineers in a truly mutual learning environment.\n\nKey Responsibilities:\n- Execute functional verification test plans\n- Participate in debug and coverage related tasks\n- Develop verification environment and architect test generators for block and system level test environment\nJob Requirements - BS/MS or higher in Computer Science, Electrical, Electronics or Computer Engineering\n- 5 to 8 years of prior work hands-on work experience in the DV domain\n- Knowledge of Verilog, System Verilog and/or C/C++\n- CPU and Cache Coherence Architecture knowledge a big plus\n- Verification and Simulation (RTL, Gate, Emulation) at core and chip levels\n- Assertion based, formal verification background a plus\n- Good communication skills and a team player\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift Not Applicable\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-05 18:30:19", "url": "http://broadcom.jobs/xml/26924815/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "18117BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 26924815}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18041BR\nJob Posting Title Engineer, Sr Principal - IC Design (Microprocessors)\nBusiness Unit Broadband Communications\nJob Description Primary responsibilities include:\n- Migrating existing circuit macros between process generations\n- Perform feasibility studies for new circuit macros\n- Design and implement new circuit macros using schematic capture and schematic based layout placement tools; create layout for critical nets in the design using script based layout tools.\n- Route and perform full verification on new circuit macros and custom cells, including functional, noise, EM/IR drop, and static timing analysis\n- Work with RTL and P&R teams to solve global timing paths and support any necessary changes to custom circuit macros\n- Create and maintain RTL for custom circuit macros\n- Design and implement standard cell based schematic driven layout of functional pieces of P&R blocks and associated critical nets\n- Work collaboratively with the circuit team to define and maintain design methodology flows and tools\n- Work collaboratively with the circuit team to define and implement process migration requirements and methodology\n- Interface with IP core development teams to specify and review circuit cell and memory block requirements and layout and provide feedback\n\n- Develop custom circuit macros for high frequency microprocessors as a key member of a small and motivated circuit team\n- Must be very familiar with dynamic and static circuit standard cell based design techniques, CAD tools, and verification including noise, EM/IR drop, and static timing analysis\n- Must be capable of carrying large functional blocks from feasibility studies through final verification with a high degree of independence\n- Able to vertically integrate with RTL and P&R teams\n- Can do attitude a must\n- Strong CMOS process knowledge a plus\nJob Requirements - BS degree with 15 years of experience, or MS with 12 years of experience, or PhD with 9 years of experience\n- 8+ years experience with custom and standard cell-based microprocessor designs, preferably with high volume parts\n- Extensive experience with dynamic logic and design hazards\n- Experience with high-speed memory and/or register file design and clock tree design and distribution\n- Programming skills; experience with Perl and scripting languages a plus\n- A working knowledge of Verilog\n- Familiarity with industry standard design tools and practices\n- Experience with Cadence Virtuoso schematic capture and layout tools as well as Synopsys PrimeTime and NanoTime timing tools a plus\n- High level of comfort working directly with layout at both the cell and block level\n- Good understanding of microprocessor architectural and micro-architectural issues and how they relate to custom circuit design issues\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift Not Applicable\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-01 19:35:14", "url": "http://broadcom.jobs/xml/26864891/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Principal - IC Design (Microprocessors)", "reqid": "18041BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 26864891}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18077BR\nJob Posting Title Engineer, Sr Staff - IC Design\nBusiness Unit Broadband Communications\nJob Description The primary purpose of this position is to analyze, project, and improve the performance of Broadcom\u2019s most advanced and innovative microprocessor.\n\nJob responsibilities include:\n\u2022 Performance modeling and simulation\n\u2022 Benchmark/workload porting, analysis, characterization and performance projection\n\u2022 Design trade-off analysis\n\u2022 Performance validation and debug\n\u2022 Competitive analysis\n\nThis job also requires interaction with various groups in order to identify and resolve performance issues.\nJob Requirements \u2022 PhD degree or Masters with experience in Computer Engineering with emphasis on computer architecture and performance analysis\n\u2022 In depth micro-architecture knowledge of multi-core, multi-thread microprocessors\n\u2022 Experience in micro-architecture modeling and simulation development\n\u2022 Experience in analyzing performance bottleneck and optimization\n\u2022 Proficient in C/C++, Assembly, and scripting language\n\u2022 Familiar with computing software, including Linux, hypervisor, and compiler\n\u2022 Prior industry experience in related fields is a big plus\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required None\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-03-01 19:34:47", "url": "http://broadcom.jobs/xml/26864879/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - IC Design", "reqid": "18077BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 26864879}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 18137BR\nJob Posting Title Staff Engineer - Processor DFT & Verification\nBusiness Unit Infrastructure and Networking\nJob Description The candidate chosen for this position will be working in the Multi-Core XLP Processor Development team, where cutting edge, industry leading designs are underway.\n\nHere you will be verifying high-quality test logic to allow easy, efficient, and effective testing and debug of chips as they move from prototype to production, helping to improve silicon yield, and improving team efficiency by automation and other techniques.\n\nYou will be exposed to multiple disciplines as a regular part of your daily job: logic design, verification, validation, test methodologies, silicon engineering.\n\nYou\u2019ll be expected to use good inter-personal skills to work across organizations to achieve the goals set with your manager.\n\nYou will be the major contributor to the RTL-level and gate-level verification efforts for the memory BIST, JTAG, and boundary scan logic for this family of products.\n\nYou will interact closely with logic design team and operations team.\n\nResponsibilities:\n\n\u2022  Be self-motivated to develop a good understand of the memory BIST, JTAG, and boundary scan logic features on the chips, and their resulting verification challenges.\n\n\u2022  Maintain the existing memory BIST (MBIST) and JTAG boundary scan test-benches. Enhance the test-benches by adding new features, improving quality and scalability. Document the test-benches to make them more usable by logic designers and new employees.\n\n\u2022  Set up the infrastructure to run weekly and monthly regressions for the test logic. Actively debug and drive the debug of failures. Track and report test-logic RTL quality over project lifetime. Identify corner cases that are not being covered, and enhance regressions to cover them.\nJob Requirements \u2022  MS EE degree.\n\n\u2022  2-3 years of recent, relevant experience are preferred.\n\n\u2022  Strong Verilog coding and comprehension skills are required.\n\n\u2022  Strong knowledge of logic design techniques is required. Actual prior logic design experience is a plus.\n\n\u2022  Prior experience with Perl scripting is required\n\n\u2022  Basic knowledge of RAM and register file internal circuitry and organization is required.\n\n\u2022  Prior verification experience is a plus.\n\n\u2022  Prior experience with memory BIST algorithms, JTAG, or boundary scan is a plus.\n\n\u2022  Longer-term interest in DFT as a career is required.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-02-22 18:34:45", "url": "http://broadcom.jobs/xml/26679383/job", "country": "United States", "company": "Broadcom", "title": "Staff Engineer - Processor DFT & Verification", "reqid": "18137BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 26679383}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 17978BR\nJob Posting Title Touch Controller Product Line Manager (PLM)\nBusiness Unit Mobile and Wireless Group\nJob Description The industry\u2019s most respected fabless communications semiconductor, software and systems innovator, Broadcom, is looking for the world\u2019s best and brightest engineers. As one of Fortune magazine\u2019s Most Admired Companies\u201d, Broadcom promotes an open work environment, embracing change, taking risks and doing the impossible every day.\nOutstanding initiative and aggressive execution is at the core of who and what we are, and we take pride in outdoing, outsmarting and outselling the competition.\n\nWith the fifth most valuable patent portfolio in the world and through the hard work and dedication of our people, Broadcom achieves a leadership position in every market we enter. If you have a passion for advancing technology, then we encourage you to apply for this exciting opportunity.\n\n* Drive product definition/feature-set and market strategy for touch controller products\n* Generate product market requirements and drive product from concept to production release\n* Analyze market trends and maintain market data (TAM, SAM)\n* Drive competitive analysis and product benchmarking activities\n* Support pre and post sales efforts to successfully secure design wins\nJob Requirements Bachelor degree in Electrical Engineering or Computer Science\n* Minimum of 5 years of experience in Product Management of semiconductor products\n* In-depth understanding of the touch market and latest technolgy trends\n* Proven product definition experience with successful product launches\n* Excellent presentation skills with ability to interface with customers\n* Strong initiative and detail oriented attitude\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 10% - 25%\nFunction Marketing\nDiscipline Product Marketing", "date_new": "2012-02-17 21:22:47", "url": "http://broadcom.jobs/xml/26600240/job", "country": "United States", "company": "Broadcom", "title": "Touch Controller Product Line Manager (PLM)", "reqid": "17978BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 26600240}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 17656BR\nJob Posting Title Engineer, Principal - IC Design\nBusiness Unit Mobile and Wireless Group\nJob Description As part of the GPS IC Team will do:\n- Microarchitecture and RTL Design of various blocks for SO Cs targeting portable consumer devices with a good understanding of system level issues\nJob Requirements - MSEE with minimum of 9 years experience in Microarchitecture and RTL Design for SOCs with a good understanding of system level issues\n- Experienced in working with other IP providers, marketing and system designers to come up with and efficient architecture.\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline IC Design", "date_new": "2012-01-28 18:17:41", "url": "http://broadcom.jobs/xml/26173709/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - IC Design", "reqid": "17656BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 26173709}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 17669BR\nJob Posting Title Touch Controller Applications Engineer\nBusiness Unit Mobile and Wireless Group\nJob Description We are looking for a strong applications engineer with expertise in the areas of design, develop, and test/debug embedded software applications and device drivers to support user input detection and tracking SOC. Candidate must be able to provide in-depth support in resolving complex software, hardware, and systems issues such as board bring-up and integrations, performance testing etc. Candidate will interface directly with customers and provide all support necessary in the areas of software development, documentation, issues resolution etc.\nJob Requirements - Masters degree or higher preferred along with at least 3 years of relevant work experience in the area of embedded firmware/software development\n- Strong knowledge of C and C++ programming languages is essential\n- Proficiency in any scripting language is required\n- Excellent oral and written communication skills is essential with experience in writing customer documentation such as application notes\n- Experience in working with customer requirements and issues is required\n- Experience with at least one mobile OS - Android, Windows/windows Mobile, iOS, etc. is required\n- Experience with embedded development is a strong plus\n- Must be self-reliant, self-motivated and able to work multiple tasks under pressure and tight timescales\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 10% - 25%\nFunction Engineering\nDiscipline Software Applications", "date_new": "2012-01-24 19:08:34", "url": "http://broadcom.jobs/xml/26077120/job", "country": "United States", "company": "Broadcom", "title": "Touch Controller Applications Engineer", "reqid": "17669BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 26077120}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 16981BR\nJob Posting Title Engineer, Sr Staff - Software Development\nBusiness Unit Mobile and Wireless Group\nJob Description We are looking for a strong embedded software developer with expertise in the areas of design, development of embedded software applications and device drivers to support multi-touch controller. Candidate must be able to develop and integrate device drivers and test applications in mobile OS' like Android/Linux, Windows Phone, and also desktop OS like Windows 7. He/she should be able to resolve complex software, hardware, and systems issues such as board bring-up and integration, and should be able to provide support for performance testing etc.\nJob Requirements 1. Masters degree or higher preferred along with at least 3 years of relevant work experience in the area of embedded software development\n2. Strong knowledge of C and C++ programming languages is essential\n3. Proficiency in any scripting language is required\n4. Excellent oral and written communication skills is essential with experience in writing application notes\n5. Experience with at least one mobile OS - Android, Windows/windows Mobile, iOS, etc. is required\n6. Capacitive touch screen controller domain knowledge is a very strong plus\n7. Exposure to GUI application development is a plus\n8. Must be self-reliant, self-motivated and able to work multiple tasks under pressure and tight timescales\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 25% - 50%\nFunction Engineering\nDiscipline Software Development", "date_new": "2011-11-22 21:05:33", "url": "http://broadcom.jobs/xml/25007151/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Sr Staff - Software Development", "reqid": "16981BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 25007151}, {"country_short": "USA", "city": "Santa Clara", "description": "Auto req ID 13176BR\nJob Posting Title Engineer, Principal - Software Development (GPS/DSP)\nBusiness Unit Mobile and Wireless Group\nJob Description We\u2019re looking for energetic and enthusiastic engineers excited about GPS technology and embedded systems. Enjoy seeing your work on the shelves of your favorite electronics store? Do you want to be part of enabling the newest and coolest gadgets? The Broadcom GPS SW Group has written code enabling GPS functionality in leading mobile phones and GPS navigation devices.\n\nWe are problem solvers. You must thrive when involved with multiple issues at the same time, and take satisfaction in solving issues as they come up. This is a great place to get exposed to a wide range of technology. You will work closely with the hardware engineers and experience full product lifecycles from pre-silicon all the way through to full software release.\n\nIn this position you will develop algorithms and software for GPS signal acquisition and tracking. You will work closely with software and hardware teams to define the implementation and verification specifications and to perform hardware bringup and system level integration. You will support low-level integration of GPS with other wireless technologies, and help define system partitioning and architecture for future generations of Broadcom's GPS and Wireless Combo chips.\nJob Requirements - Typically requires an MSEE degree and 6 years of experience or a PhD and 3 years of related experience\n- Extensive experience in the design, simulation, testing, and implementation of practical DSP algorithms for communication or satellite navigation systems (Emphasis is on signal acquisition and tracking, data decoding, multipath mitigation with specific GPS knowledge is a plus)\n- Background in fixed point design, implementation of regression tests, generation of test vectors for hardware verification, coding of algorithms in firmware in C/C++\n- Ability to interface well with hardware, RF, and embedded software teams\n- Some understanding of HW/SW architecture issues\n- Proficiency in Matlab\n- Strong debugging/trouble-shooting skills and the ability of analyze field data\n- Excellent work ethic, dependable, and responsible\n- Must be a flexible self-starter who can ramp up with new technologies quickly\n- Imaginative, motivated, and able to work effectively under pressure\n- Strong logical and creative problem-solving skills, good oral and written communication skills, and excellent analytical skills\nCountry United States\nState/Province California\nCity/Town Santa Clara\nShift 1st Shift - Day\nPercent of Travel Required 5% - 10%\nFunction Engineering\nDiscipline Software Development", "date_new": "2011-04-01 19:14:58", "url": "http://broadcom.jobs/xml/20478598/job", "country": "United States", "company": "Broadcom", "title": "Engineer, Principal - Software Development (GPS/DSP)", "reqid": "13176BR", "state": "California", "state_short": "CA", "location": "Santa Clara, CA", "uid": 20478598}]