Auto req ID 17784BR
Job Posting Title Physical Design Sr. Staff Engineer
Business Unit Mobile and Wireless Group
Job Description Broadcom is developing solutions supporting the next generation of 3G and 4G high-speed mobile technologies. As part of the CellAirity™ Mobile Platform, Broadcom offers a family of HSDPA (High-Speed Downlink Packet Access), WCDMA (Wideband Code Division Multiple-Access), EDGE (Enhanced Data Rates for GSM Evolution), GPRS (General Packet Radio Services) and GSM (Global System for Mobile Communication) baseband processors for use in cellular handsets, PC cards and other wireless-enabled consumer electronics.

As wireless handsets and portable media players emerge as the dominant platform for mobile multimedia, Broadcom offers a family of mobile multimedia processors offering the ability to build next generation handheld devices supporting the latest in multimedia applications such as audio and video telephony, messaging, interactive gaming, location-based services and improved Web browsing.

Broadcom is helping to build the next generation of mobile devices through our broad portfolio of industry-leading technologies for Bluetooth®, Wi-Fi®, VoIP, FM radio, DVB-H mobile TV, multimedia and other emerging technologies.

This senior-level role will be part of our experienced and motivated mobile & wireless team responsible for cellular product.

In this role, your main responsibilities will be the integration IP from RTL to GDS.

Specific responsibilities include:
Logic/physical synthesis
Floorplanning
Timing driven place and route
Static timing analysis
Signal integrity analysis
Physical verification.

You will also have an opportunity to define next generation physical implementation methodology, signal integrity analysis (Power, Noise) and logical/physical synthesis for high speed processor and SoC design.
Job Requirements Typically requires a BS degree and 9 years of experience or an MS degree and 6 years of experience or a PhD and 3 years of experience.

You should have hand-on experience with RTL to GDSII flow, DFM and signal integrity in deep submicron process.

Technical expertise at timing driven P&R, static timing analysis and PERL/TCL scripting is a must.
Solid experience in full synthesis to GDS flow

Hand-on experience in ATOP, Cadence & Synopsys tools is essential

Experience in DFM and signal integrity analysis

Experience of 28nm/20nm design methodology preferred.

Self motivated, with good verbal/written communication skills and able to work well in a small but growing team

Ability to work under intensive pressure and tight schedule
Country United States
State/Province California
City/Town Sunnyvale
Shift 1st Shift - Day
Percent of Travel Required 5% - 10%
Function Engineering
Discipline IC Design